OPTIREG™ SBC TLE9274QXV33
Serial Peripheral Interface
SYS_STATUS_CTRL
System status control (Address 001 1110B)
POR Value: 0000 0000B;
Restart Value/Soft Reset Value: xxxx xxxxB
7
6
5
4
3
2
1
0
SYS_STAT_7 SYS_STAT_6 SYS_STAT_5 SYS_STAT_4 SYS_STAT_3 SYS_STAT_2 SYS_STAT_1 SYS_STAT_0
r
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
rw
Description
SYS_STAT
7:0
System status control byte (bit0=LSB; bit7=MSB)
Dedicated byte for system configuration, access only by
microcontroller. No SBC functions
Notes
1. The SYS_STATUS_CTRL register is an exception for the default values, i.e. it will keep its configured value
even after a Soft Reset.
2. This byte is intended for storing system configurations of the ECU by the microcontroller and it is writable in
SBC Normal and Stop mode. The byte is not accessible by the SBC and is also not cleared after Fail-Safe or
SBC Restart mode. It allows the microcontroller to quickly store system configuration without losing the data.
Datasheet
108
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
