OPTIREG™ SBC TLE9274QXV33
Serial Peripheral Interface
Field
Bits
7
Type
Description
Reserved
LIN1_FAIL
r
Reserved, always reads as 0
6:5
rc
LIN failure status
00B , No error
01B , LIN TSD shutdown, also TSD1 is signaled
10B , LIN_TXD_DOM: TXDLIN dominant time out
11B , LIN_BUS_DOM: BUS dominant time out
Reserved
CAN_FAIL
4:3
2:1
r
Reserved, always reads as 0
rc
CAN failure status
00B , No error
01B , CAN TSD shutdown, also TSD1 signaled
10B , CAN_TXD_DOM: TXDCAN dominant time out
11B , CAN_BUS_DOM: BUS dominant time out
VCAN_UV
Notes
0
rc
Undervoltage VCAN supply
0B
1B
, Normal operation
, VCAN supply undervoltage detected. Transmitter disabled
1. CAN and LIN recovery conditions:
1.) TXD Time Out: TXD goes HIGH or transmitter is set to wake capable or switched off.
2.) Bus dominant time out: Bus will become recessive or transceiver is set to wake capable or switched off.
3.) Supply undervoltage: as soon as the threshold is crossed again, i.e. VLIN > VS_UV for LIN and VCAN >
VCAN_UV for CAN.
4.) In all cases (also for TSD shutdown): to enable the bus transmission again, TXD needs to be HIGH for a
certain time (transmitter enable time).
2. The VCAN_UV comparator is enabled if the CAN is CAN Normal mode or CAN Receive-Only mode or CAN Wake
Capable after one valid WUP is detected.
BUS_STAT_2
Bus communication status (Address 100 0101B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0xxx xxx0B
7
6
5
4
3
2
1
0
reserved
LIN4_FAIL_1 LIN4_FAIL_0 LIN3_FAIL_1 LIN3_FAIL_0 LIN2_FAIL_1 LIN2_FAIL_0
reserved
r
r
rc
rc
rc
rc
rc
rc
r
Field
Bits
Type
Description
Reserved
7
r
Reserved, always reads as 0
Datasheet
112
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
