OPTIREG™ SBC TLE9274QXV33
Serial Peripheral Interface
Field
Bits
Type
Description
TIMER_WU
4
rc
Wake up via timer
0B
1B
, No Wake up
, Wake up
Reserved
WK_WU
3:1
0
r
Reserved, always reads as 0
rc
Wake up via WK
0B
1B
, No Wake up
, Wake up
WK_STAT_2
Wake-up source and information status (Address 100 0111B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 xxxxB
7
6
5
4
3
2
1
0
reserved
reserved
reserved
reserved
LIN4_WU
LIN3_WU
LIN2_WU
LIN1_WU
r
r
r
r
r
rc
rc
rc
rc
Field
Bits
Type
Description
Reserved
LIN4_WU
7:4
3
r
Reserved, always reads as 0
rc
Wake up via LIN4 bus
0B
1B
, No Wake up
, Wake up
LIN3_WU
LIN2_WU
LIN1_WU
2
1
0
rc
rc
rc
Wake up via LIN3 bus
0B
1B
, No Wake up
, Wake up
Wake up via LIN2 bus
0B
1B
, No Wake up
, Wake up
Wake up via LIN1 bus
0B
1B
, No Wake up
, Wake up
WK_LVL_STAT
WK input level (Address 100 1000B)
POR / Soft Reset Value: x100 000xB;
Restart Value: x1x0 000xB
7
6
5
4
3
2
1
0
TEST
reserved CFG2_STATE reserved
reserved
reserved
reserved
WK
r
r
r
r
r
r
r
r
r
Datasheet
114
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
