OPTIREG™ SBC TLE9274QXV33
Serial Peripheral Interface
Field
Bits
Type
Description
VCC1_SC
2
rc
VCC1 short to GND detection
0B
1B
, No short
, VCC1 short to GND detected
Reserved
VCC1_UV
1
0
r
Reserved, always reads 0
rc
VCC1 undervoltage detection
0B
1B
, No VCC1 undervoltage
, VCC1 undervoltage detected
Notes
1. When VCC1 is OFF (for example in SBC Sleep mode), the bits VCC1_SC and VCC1_UV will not be set.
2. When VCC2 is OFF, the bit VCC2_UV and VCC2_OT will not be set.
3. When all LIN’s are wake capable or OFF, VLIN_UV will not be set.
THERM_STAT
Thermal protection status (Address 100 0010B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0xxxB
7
6
5
4
3
2
1
0
reserved
reserved
reserved
reserved
reserved
TSD2
TSD1
TPW
r
r
r
r
r
r
rc
rc
rc
Field
Bits
Type
Description
Reserved
TSD2
7:3
2
r
Reserved, always reads as 0
rc
TSD2 thermal shutdown detection
0B
1B
, No TSD2 fail
, TSD2 thermal shutdown detected (leading to SBC Fail-Safe
mode)
TSD1
TPW
1
0
rc
rc
TSD1 thermal shutdown detection
0B
1B
, No TSD1 fail
, TSD1 thermal shutdown detected
Thermal prewarning
0B
1B
, No thermal prewarning
, Thermal prewarning detected
DEV_STAT
Device information status (Address 100 0011B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
FO_ON_
STATE
DEV_STAT_1 DEV_STAT_0 RO_CL_HIGH FSI_FAIL
WD_FAIL_1 WD_FAIL_0
rh rh
SPI_FAIL
r
rc
rc
rc
rc
rc
rc
Datasheet
110
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
