OPTIREG™ SBC TLE9274QXV33
Serial Peripheral Interface
Field
LIN2
Bits
Type
Description
1:0
rwh
LIN module mode
00B , LIN2 OFF
01B , LIN2 is wake capable
10B , LIN2 Receive-Only mode
11B , LIN2 Normal mode
Note: In case either CAN or LIN transceivers are configured to ‘11’ while going to SBC Stop or Sleep mode, they
will be automatically set to wake capable (‘01’). However, the SPI bits will stay unchanged, i.e. once the
SBC returns to Normal mode, the previous state is recovered again (‘11’).The Receive-Only mode (‘10’) has
to be selected by purpose before entering SBC Stop mode. For more details, refer to Figure 25.
WK_CTRL_1
Wake input control (Address 000 0110B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0x00 0000B
7
6
5
4
3
2
1
0
TIMER1_WK_
EN
WD_STM_
EN_1
reserved
reserved
reserved
reserved
reserved
reserved
r
r
rw
r
r
r
rwh
r
r
Field
Reserved
Bits
Type
Description
7
r
Reserved, always reads as 0
Timer1 wake source control
TIMER1_WK 6
rw
_EN
0B
1B
, Timer1 wake disabled
, Timer1 is enabled as a wake source
Reserved
5:3
r
Reserved, always reads as 0
Watchdog activation during SBC Stop mode
WD_STM_
EN_1
2
rwh
0B
1B
, Watchdog is active in Stop mode
, Watchdog is deactivated in Stop mode
Reserved
1:0
r
Reserved, always reads as 0
WK_CTRL_2
Wake source control (Address 000 0111B)
POR / Soft Reset Value: 0000 0001B; Restart Value: 0000 000xB
7
6
5
4
3
2
1
0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
WK_EN
r
r
r
r
r
r
r
r
rw
Field
Bits
7:1
Type
Description
Reserved
r
Reserved, always reads as 0
Datasheet
106
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
