OPTIREG™ SBC TLE9274QXV33
Serial Peripheral Interface
Field
Bits
Type
Description
MAX_3_RST
3
rw
Limit number of resets due to a watchdog failure
0B
1B
, Always generate a reset in case of WD fail
, After 3 consecutive resets due to WD fail, no further reset is
generated
WD_TIMER 2:0
rwh
Watchdog timer period
000B , 10 ms
001B , 20 ms
010B , 50 ms
011B , 100 ms
100B , 200 ms
101B , 500 ms
110B , 1s
111B , reserved
Note: See also Chapter 13.2.4 for more information on disabling the watchdog SBC Stop mode.
BUS_CTRL_1
Bus control (Address 000 0100B)
POR / Soft Reset Value: 0010 0000B;
Restart Value: xxxx x0xxB
7
6
5
4
3
2
1
0
LIN_FLASH
LIN_LSM
LIN_TXD_TO
LIN1_1
LIN1_0
reserved
CAN_1
CAN_0
r
rw
rw
rw
rwh
rwh
r
rwh
rwh
Field
Bits
Type
Description
LIN_FLASH
7
rw
LIN flash programming mode
0B
1B
, Slope control mechanism active
, Deactivation of slope control for baud rates up to 115 kBaud
LIN_LSM
6
rw
LIN LOW-slope mode selection
0B
1B
, LIN Normal-slope mode is activated
, LIN Low-slope mode is activated
LIN_TXD_
TO
5
rw
LIN TXD time-out control
0B
1B
, TXDLIN time-out feature disabled
, TXDLIN time-out feature enabled
LIN1
4:3
rwh
LIN module mode
00B , LIN1 OFF
01B , LIN1 is wake capable
10B , LIN1 Receive-Only mode
11B , LIN1 Normal mode
Reserved
2
r
Reserved, always reads as 0
Datasheet
104
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
