PEB 2091
PEF 2091
Operational Description
4
Operational Description
In chapters 2 and 3 the pins and user’s interfaces of the IEC-Q are described in detail.
Using this information, this chapter describes the interaction between these interfaces in
detail. The approach used is to describe how IEC-Q features can be accessed using the
different user interfaces, described in chapter 3.
Most of the IEC-Q features can be accessed via IOM®-2 interface. In the microprocessor
mode the processor interface provides almost unlimited access to the IOM®-2 channels
in upstream and downstream directions, and consequently to most of the IEC-Q
features. This µP access to the IOM®-2 interface is described in section 4.1.
Access to the U-interface is the scope of section 4.2. A detailed description is given
about the possibilities of (always indirect) access to each channel of the U-interface and
the behavior of the IEC-Q in each mode (e.g. NT, LT, EOC Auto and Transparent
modes).
Sections 4.3 and 4.4 cover the whole issue of activation and deactivation procedures
and control. Section 4.3 describes layer 1 activation and deactivation procedures of
different configurations. Section 4.4 describes the activation and deactivation control of
the different modes of the IEC-Q itself.
Access to numerous maintenance features is discussed in sections 4.5 through 4.9. This
includes monitoring transmission quality, features supporting test loop-backs defined by
the national PTTs, power status monitoring features as well as chip internal testing
features.
Features of the power controller interface are described in section 4.10 which applies
only in the stand-alone mode.
Section 4.11 applies only to the microprocessor mode if used in the NT or the TE mode,
and describes how to program and access the S/G and BAC bit features which can be
used in applications like Wireless Local Loop and D-Channel arbitration.
Semiconductor Group
96
Data Sheet 01.99
INFINEON [ Infineon ]
