PEB 2091
PEF 2091
Operational Description
4.1
Microprocessor Access to IOM®-2 Channels
Note 27: This chapter applies only in µP mode.
In µP mode the microcontroller has access to the IOM®-2 channels via the processor
interface (PI) and registers.
FSC
-2
U
IOM R -2
U
PI
ITS10193
Figure 39
Access to IOM®-2 Channels (µP mode)
The processor interface can be understood as an intelligent switch between IOM®-2 and
the transceiver core. It handles D, B1, B2, C/I and Monitor-channel data. The data can
either be transferred directly between IOM®-2 and the transceiver core, or be controlled
via the PI. The PI acts as an additional participant to the Monitor Channel.
Switching directions are selected by setting the register SWST as indicated below:
SWST-Register
WT
B1
B2
D
CI
MON
BS
SGL
• Setting one of the 5 bits B1, B2, D, CI, or MON of SWST to "1" enables the µP access
to the corresponding data.
• Setting the bits listed above to "0" directly passes the corresponding data from IOM®-2
to the transceiver core and vice versa.
Refer also to "SWST-Register", page 220 for more details. The default value after
hardware reset is "0" at all 8 positions.
Semiconductor Group
97
Data Sheet 01.99
INFINEON [ Infineon ]
