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PEB2091NV5.3 参数 Datasheet PDF下载

PEB2091NV5.3图片预览
型号: PEB2091NV5.3
PDF下载: 下载PDF文件 查看货源
内容描述: 集成电路通信( ISDN Echocancellation电路) [ICs for Communications(ISDN Echocancellation Circuit)]
分类和应用: 电信集成电路综合业务数字网通信
文件页数/大小: 299 页 / 1531 K
品牌: INFINEON [ Infineon ]
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PEB 2091  
PEF 2091  
Functional Description  
3.11  
Power Status  
Two pins PS1 and PS2 are available for comfortably surveying and controlling the power  
status.  
In addition, if the stand-alone mode is being used, a third pin (DISS) is also available.  
In NT mode, power status bits 1 and 2 (PS1/2) are used to monitor both primary and  
secondary NT power supply. This information is transferred via the overhead bit channel  
to the exchange side. For operational details, see "Monitoring Primary and Secondary  
NT Power Supply", page 194.  
In LT mode the first power status bit (PS1) is used to monitor the remote power feed  
circuit of the subscriber line. For operational details, see "Monitoring Remote Power  
Feed Circuit in LT Modes", page 194.  
The pin PS2 provides a serial interface in order to read in the value of the current fed to  
the subscriber line by the power controller. This function is available only in combination  
with a power controller which supports this feature (the IEPC does not). For operational  
details, see "Monitoring Power Feed Current in LT Modes", page 194.  
If the stand-alone mode is being used the following features are also available.  
In the NT and TE modes the output pin disable (DISS) is set to (1) if the EOC-command  
"close complete loop" (LBBD) has been detected by the NT. This function is only  
available in EOC Auto mode. It may be used to test a secondary power source (e.g.  
battery check). For operational details, see "Access to Pin DISS", page 195.  
In the LT modes the DISS-pin is used for switching off the remote power supply of the  
subscriber line. For operational details, see "Access to Pin DISS", page 195.  
3.12  
Undervoltage Detection  
Note 24: This chapter applies only in the microprocessor mode (PMODE = "1").  
The undervoltage detector is enabled by setting the ADF:UVD bit to "1", see  
"ADF-Register", page 219. Note that the default setting of this bit after power on will be  
"1", i.e. the undervoltage detection feature will be activated. It activates the reset signal  
if the supply voltage drops below the threshold UL (typically 4.21 V, see Figure 37 below  
and "Undervoltage Detection Timing", page 280).  
It also acts as power on reset by creating a reset pulse on pin RST if the supply voltage  
rises above UH (typically 4.30 V). It then stays inactive until the supply voltage drops  
again below the threshold level UL (see also "Power On Reset (POR)", page 93, for more  
information).  
Semiconductor Group  
92  
Data Sheet 01.99  
 
 
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