PEB 2091
PEF 2091
Operational Description
4.1.3
C/I Channel Access
Setting SWST:CI to "1" enables the microprocessor to access C/I-commands and
indications between IOM®-2 and the transceiver core.
A change in two consecutive frames (double last look) in the C/I-channel on IOM®-2 is
indicated by an interrupt ISTA:CICI. The received C/I-command can be read from
register CIRI. A change in the C/I-channel coming from the transceiver core is indicated
by an interrupt ISTA:CICU. The new C/I-indication can be read from register CIRU.
Note 30: The term C/I-indication always refers to a C/I-code coming from the
transceiver core, whereas the term C/I-command refers to a C/I-code going
into the transceiver core.
A C/I-code going to the transceiver core has to be written into the CIWU-register. A
C/I-code to IOM®-2 has to be written into the CIWI-register. The contents of both
registers (CIWU and CIWI) will be transferred at the next available IOM®-2 frame. The
registers are not cleared after the transfer. Therefore, it is possible to continuously send
C/I codes to IOM®-2 or the transceiver core by only writing the code into the register
once.
C/I-commands to the transceiver core have to be applied at least for two IOM®-2 frames
(250 µs) to be considered as valid.
For more information see section 5.2.7, page 217 and thereafter. See also "Interrupt
Structure", page 209.
In TE mode (i.e. 1.536 MHz DCL), the ADF2:TE1 bit is used to direct the C/I-channel
access either to IOM®-2 channel 0 (ADF2:TE1 = 0, default) or to IOM®-2 channel 1 of
the IOM®-2 terminal structure (ADF2:TE1 = 1), see Figure 41. This allows to program
terminal devices such as the ARCOFI® via the processor interface of the IEC-Q. The C/I
code going to IOM®-2 is 4 bits long if it is written to IOM®-2 channel 0 (ADF2:TE1 = 0).
If written to IOM®-2 channel 1 this C/I code is 6 bits long (ADF2:TE1 = 1). If the
ADF2:TE1 bit is 1, the C/I Channel on IOM®-2 channel 0 is passed transparently from
the IOM®-2 interface to the transceiver core.
See also "ADF2-Register", page 214 for more information about this register.
Semiconductor Group
100
Data Sheet 01.99
INFINEON [ Infineon ]
