PEB 2091
PEF 2091
Operational Description
Note 28: The microprocessor interface provides almost unlimited access
possibilities to the active IOM®-2 channel. One important consequence
is that all actions described in this document involving the active
channel of the IOM®-2 interface or parts of it (e.g. B, D, Monitor and C/I
channels) can be also performed using the PI.
In the IOM®-2 Master mode proper function using the microprocessor
interface is possible even if the IOM®-2 interface is omitted. In this case
pin DIN should be clamped to ’1’.
In the IOM®-2 Slave mode the IOM®-2 clocks can not be omitted. They
are needed for internal data synchronization reasons. If pin DIN is not
used, it should be clamped to ’1’. If pin DOUT is not used it should be
left open.
4.1.1
B-Channel Access
Setting SWST:B1 (B2) to "1" enables the microprocessor to access B1 (B2)-channel
data between IOM®-2 and the transceiver core.
Eight registers (see Table 14) handle the transfer of data from IOM®-2 to the µP, from
the µP to IOM®-2, from the µP to transceiver core and from transceiver core to the µP:
Table 14
Register
WB1U
RB1U
WB1I
B1/B2-Channel Data Registers
Function
write B1-channel data to transceiver core
read B1-channel data from transceiver core
write B1-channel data to IOM®-2
read B1-channel data from IOM®-2
write B2-channel data to transceiver core
read B2-channel data from transceiver core
write B2-channel data to IOM®-2
read B2-channel data from IOM®-2
RB1I
WB2U
RB2U
WB2I
RB2I
For more informations about these registers, refer to "B-Channel Access Registers",
page 221. Every time B-channel bytes arrive, an interrupt ISTA:B1 or ISTA:B2
respectively is created. It is cleared after the corresponding registers have been read.
ISTA:B1 is cleared after RB1U and RB1I have been read. ISTA:B2 is cleared after RB2I
and RB2U have been read. After an interrupt the data in RB1U and RB1I is stable for
125µs. For more informations, refer to "Interrupt Structure", page 209.
Semiconductor Group
98
Data Sheet 01.99
INFINEON [ Infineon ]
