PEB 2091
PEF 2091
Functional Description
Vdd
UH
UL
1.0V
RST
Figure 37
UVD Control of Pin RST
While the supply voltage is below threshold UL, the microcontroller clock MCLK is
stopped and the MCLK output remains low1). If the supply voltage falls below threshold
UL, the clock is stopped immediately which may result in one shorter high period of the
clock signal.
Note 25: For power saving reasons, this function is not available in power down.
Still pin RST will not float in this state and the power on reset function
is still available, see 3.14 below.
3.13
Watchdog Timer
Note 26: This chapter applies only in the microprocessor mode (PMODE = "1").
The watchdog is enabled by setting the SWST:WT bit to "1", see "SWST-Register", page
220. The value of SWST:WT after hardware reset (RES = ’0’) is "0".
After the microcontroller has enabled the watchdog timer it has to write the bit patterns
"10" and "01" in ADF:WTC1 and ADF:WTC2 within a period of 132 ms, see
"ADF-Register", page 219. If it fails to do so, a reset signal of 5 ms at pin RST is
generated. The clock at pin MCLK remains active during this reset.
3.14
Power On Reset (POR)
The PEB/F 2091 is equipped with a POR feature. During power on or power off, an
internal reset will be generated if the POR threshold (between 2.5 V and 4.5 V) is
1) The behavior of the microcontroller clock MCLK is not specified below the supply voltage of 4.0
Volt.
Semiconductor Group
93
Data Sheet 01.99
INFINEON [ Infineon ]
