PEB 2091
PEF 2091
Operational Description
4.1.2
D-Channel Access
Setting SWST:D to "1" enables the microprocessor to access D-channel data between
the IOM®-2 and the transceiver core.
Four registers (see Table 15) handle the transfer of data from IOM®-2 to the µP, from the
µP to IOM®-2, from the µP to transceiver core and from transceiver core to the µP. See
"D-Channel Access Registers", page 221 for more details about these registers.
.
Table 15
Register
DWU
D-Channel Data Registers
Function
write D-channel data to transceiver core
read D-channel data from transceiver core
write D-channel data to IOM®-2
read D-channel data from IOM®-2
DRU
DWI
DRI
Two 2-bit FIFOs of length 4 collect the incoming D-channel packets from IOM®-2 and U.
Every fourth IOM®-2-frame when they are filled, an interrupt ISTA:D is generated and
the contents of the FIFOs are shifted in parallel to DRU and DRI respectively. DRU and
DRI have to be read before the next interrupt ISTA:D can occur, otherwise 8 bits will be
lost. DWU and DWI have to be loaded with data for 4 IOM®-2-frames. Data in DWU and
DWI is assumed to be valid at the time ISTA:D occurs (see also "Interrupt Structure",
page 209). The register contents are shifted in parallel into two 2-bit FIFOs of length four,
from where the data is put to IOM®-2 and transceiver core respectively during the
following 4 IOM®-2-frames. During this time, new data can be placed on DWU and DWI.
DWU and DWI are not cleared after the data was passed to the FIFOs. That is, a byte
may be put into DWU or DWI once and continuously passed to IOM®-2 or transceiver
core, respectively. Figure 40 illustrates this procedure:
Arriving D-Channel Bits
2 Bits
DRU or DRI
DWU or DWI
Leaving D-Channel Bits
ITD08120
Figure 40
Procedure for the D-Channel Processing
Note 29: Default of DWU, DWI, DRU and DRI after reset is "FFH".
Semiconductor Group
99
Data Sheet 01.99
INFINEON [ Infineon ]
