PEB 2091
PEF 2091
Functional Description
The clock MCLK is delivered during reset (except for power-on and undervoltage
detection).
Table 13 shows that the output pin RST is controlled by power-on reset, undervoltage
detection and the watchdog timer. Figure 38 illustrates the reset sources that have an
impact on pin RST.
Undervoltage
Detection
67 ms
60-70 ms
RST
Power-On Reset
Watchdog
+
5 ms
Figure 38
3.16
Reset Sources
Test Block
In stand-alone mode the two pins TP and TP1 are used for internal manufacturing device
tests. In microprocessor mode only pin TP is used for device test. Test pins are not
defined for normal system operation, as described in this document, and should
therefore be left unconnected.
Semiconductor Group
95
Data Sheet 01.99
INFINEON [ Infineon ]
