PEB 2091
PEF 2091
Functional Description
S/G Status Indication on Pin SG
If one of the packages M-QFP-64 or T-QFP-64 is being used the S/G bit status
information will be additionally provided on pin SG, see "Miscellaneous Function Pins",
page 46. This feature is not available in the package P-LCC-44.
3.10
Power Controller Interface
Note 23: This chapter applies only in stand-alone mode.
A power controller interface is implemented in the IEC-Q to provide comfortable access
to peripheral circuits which are not connected directly to the microprocessor. Because
this interface was specifically designed to support the ISDN Exchange Power Controller
IEPC (PEB 2025) it is referred to as "Power Controller Interface". Despite this dedication
to the IEPC, the controller interface is just as suited for other general-purpose
applications.
The interface structure consists of
– 3 bit data bus PCD0 ... 2
– 2 bit address bus PCA0,1
– 3 control signals PCRD and PCWR
– 1 interrupt facility INT
See also "Power Controller Pins", page 36, for information about pin configurations.
The address bits are latched, they may therefore in general interface applications be
used as output lines. For general interface inputs each of the three data bits is suitable.
Read and write operations are performed via MON-8 commands. Three inputs and two
outputs are thus available to connect external circuitry.
The interrupt pin is edge sensitive. Each change of level at the pin INT will initiate a
C/I-code INT lasting for four IOM®-2-frames. Interpretation of the interrupt cause and
resulting actions need to be performed by the control unit.
For informations about communication with the power controller interface, see "Access
to Power Controller Interface", page 196.
For informations about dynamic characteristics of the power controller interface, see
"Power Controller Interface Timing", page 277.
Semiconductor Group
91
Data Sheet 01.99
INFINEON [ Infineon ]
