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PEB2091NV5.3 参数 Datasheet PDF下载

PEB2091NV5.3图片预览
型号: PEB2091NV5.3
PDF下载: 下载PDF文件 查看货源
内容描述: 集成电路通信( ISDN Echocancellation电路) [ICs for Communications(ISDN Echocancellation Circuit)]
分类和应用: 电信集成电路综合业务数字网通信
文件页数/大小: 299 页 / 1531 K
品牌: INFINEON [ Infineon ]
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PEB 2091  
PEF 2091  
Functional Description  
3.8  
Microprocessor Interface  
Note 21: This Interface is only available in the microprocessor mode.  
The parallel/serial microprocessor interface can be selected to be either of the  
1. Siemens/Intel non-multiplexed bus type with control signals CS, WR, RD  
2. Motorola type with control signals CS, R/W, DS  
3. Siemens/Intel multiplexed address/data bus type with control  
signals CS, WR, RD, ALE  
4. Serial mode using control signals CDIN, CDOUT, CCLK and CS.  
The selection is performed via pins ALE/CCLK and SMODE as follows:  
Table 12  
Microprocessor Interface Modes  
ALE  
0
SMODE  
Siemens/Intel non-Mux  
Motorola  
x
x
0
1
1
Siemens/Intel Mux  
Serial  
edge  
edge  
The occurrence of an edge on ALE/CCLK, either positive or negative, at any time during  
the operation immediately selects interface type 3 or 4. A return to one of the other  
interface types is possible only if a hardware reset is issued.  
The timing of the different microprocessor bus types is given in sections 8.7.1, page 269  
for the parallel bus type and in section 8.7.2, page 273, for the serial bus type.  
3.9  
S/G Bit and BAC bit Control  
Note 22: This chapter applies only in the µP-TE mode (see "Basic Operating  
Mode", page 50).  
If DCL = 1.536 MHz the IOM®-2 interface consists of three IOM®-2 channels (see  
"Terminal Timing Mode", page 73). The last octet of an IOM®-2 frame includes the S/G  
and the BAC bit. Either or both bits can be used in various applications including  
• the D-channel arbitration in a PBX via an ELIC® on the line card  
• the synchronization of a base station in wireless local loop applications  
The S/G bit is always written and never read by the IEC-Q. Its value depends on the last  
received EOC-command and on the status of the BAC bit. The processing mode for the  
S/G bit is selected via bits SWST:BS, SWST:SGL and ADF:CBAC (see "ADF-Register",  
page 219). A detailed operational description of the S/G bit control in all modes is  
provided in "S/G Bit and BAC Bit Operations", page 198.  
Semiconductor Group  
90  
Data Sheet 01.99