PEB 2091
PEF 2091
Functional Description
IEC-Q issues all IOM®-2 clocks. An external clock generation circuit is not required.
Information on the U-interface is transmitted synchronous to the system clock.
XIN/XOUT
A free running crystal or other clock source should provide a 15.36-MHz base clock (see
also “External Circuitry” on page 249 for more informations about crystal properties).
CLS Clock
In these modes the IEC-Q issues a 7.68-MHz clock signal. This clock signal is not
synchronous to the received U-interface signal. It is also available in power down.
3.7.6
Microprocessor Clock Output
Note 20: This clock is only available in the µP mode.
The microprocessor clock on the MCLK-output. Four clock rates are provided by a
programmable prescaler in the ADF register (see "ADF-Register", page 219). These are
7.68 MHz, 3.84 MHz, 1.92 MHz and 0.96 MHz. The default value after reset is 3.84 MHz.
Switching between the clock rates is realized without spikes. The oscillator remains
active all the time. The clock is synchronized to the 15.36 MHz clock at the XIN pin.
Semiconductor Group
89
Data Sheet 01.99
INFINEON [ Infineon ]
