Register Description
4.2.18 S, Q Channel Transmit Register
SQXR
Write
Address 3B
H
Value after reset: TE/LT-T mode (pin M1 = 0) : 0F
H
LT-S/NT mode (pin M1 = 1) : 00
H
7
0
0
0
0
SQIE SQX1 SQX2 SQX3 SQX4
SQIE
S, Q Interrupt Enable
Generation of CIR0: SQC status (and the accompanying CISQ interrupt is
enabled (1) or masked (0).
SQX1-4 Transmitted S/Q Bits
TE/LT-T mode (pin M1 = 0): transmitted F bits in frames 1, 6, 11 and 16,
A
respectively.
LT-S/NT mode (pin M1 = 1): transmitted S bits in frames 1, 6, 11 and 16,
respectively.
Semiconductor Group
229