Register Description
A falling edge on the EAW line generates an SAW interrupt (EXIR).
When the RSS-bit in the CIXR register is zero, a falling edge on the EAW line
(Subscriber Awake) or a C/I code change (Exchange Awake) initiates a reset
pulse.
When the RSS-bit is set to one a reset pulse is triggered only by the expiration
of the watchdog timer (see also CIXR register description).
Note: The TSF-bit will be cleared only by hardware reset.
TBA2-0 TIC Bus Address
Defines the individual address for the ISAC-S on the IOM TIC bus
(see chapter 2.3.9).
This address is used to access the C/I and D channel on the IOM.
Note: One device liable to transmit in C/I and D fields on IOM should always be given the
address value "7".
ST1
ST0
SC1
Synchronous Transfer 1
When set, causes the ISAC-S to generate an SIN interrupt status (ISTA register) at
the beginning of an IOM frame.
Synchronous Transfer 0
When set, causes the ISAC-S to generate an SIN interrupt status (ISTA register) at
the middle of an IOM frame.
Synchronous Transfer 1 Completed
After an SIN interrupt the processor has to acknowledge the interrupt by setting the
SC1-bit before the middle of the IOM frame, if the interrupt was originated from a
Synchronous Transfer 1 (ST1).
Otherwise an SOV interrupt (EXIR register) will be generated.
SC0
Synchronous Transfer 0 Completed
After an SIN interrupt the processor has to acknowledge the interrupt by setting the
SC0-bit before the start of the next IOM frame, if the interrupt was originated from a
Synchronous Transfer 0 (ST0).
Otherwise an SOV interrupt (EXIR register) will be generated.
Note: ST0/1 and SC0/1 are useful for synchronizing MP accesses and
receive/transmit operations.
Semiconductor Group
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