Register Description
1:
Watchdog Timer
The expiration of the watchdog timer generates a reset pulse.
The watchdog timer will be reset and restarted, when two specific bit
combinations are written in the ADF1 register within the time period of 128 ms
(see also ADF1 register description).
After a reset pulse generated by the ISAC-S and the corresponding interrupt
(WOV, SAW or CISQ) the actual reset source can be read from the ISTA and
EXIR register.
BAC
Bus Access Control
Only valid if the TIC-bus feature is enabled (MODE:DIM2-0).
If this bit is set, the ISAC-S will try to access the TIC-bus to occupy the C/I channel
even if no D channel frame has to be transmitted. It should be reset when the access
has been completed to grant a similar access to other devices transmitting in that IOM
channel.
Note: Access is always granted by default to the ISAC-S/ICC with TIC bus address
(TBA2-0, STCR register) "7", which has the lowest priority in a bus configuration.
CODX0 C/I Code 0 Transmit
Code to be transmitted in the C/I channel / C/I channel 0.
(refer to chapter 3.3.2)
4.3.4
MONITOR Receive Channel 0
MOR0
Read
Address 32
H
7
0
Contains the MONITOR data received in IOM MONITOR channel/
MONITOR channel 0 according to the MONITOR channel protocol.
4.3.5
MONITOR Transmit Channel 0
MOX0
Write
Address 32
H
7
0
Contains the MONITOR data to be transmitted in IOM MONITOR channel/
MONITOR channel 0 according to the MONITOR channel protocol.
4.3.6
Command/Indication Receive 1
CIR1
Read
Address 33
H
Semiconductor Group
233
INFINEON [ Infineon ]
