Register Description
4.3
Special Purpose Registers: IOM®-2 Mode
The following register description is only valid if IOM-2 is selected (ADF2:IMS-1).
For IOM-1 mode refer to chapter 4.2.
4.3.1
Serial Port Control Register
spcr
Read/Write Address 30
H
Value after reset: 00
H
7
0
SPU
0
SPM
TLP
C1C1 C1C0 C2C1 C2C0
Important Note After a hardware reset the pins SDAX/SDS1 and SCA/FSD/SDS2 are both
"low" and have the functions of SDS1 and SDS2 in terminal timing mode
(since SPM = 0), respectively, until the SPCR is written to for the first time.
From that moment on, the function taken on by these pins depends on the
state of the IOM Mode Select bit IMS (ADF2 register).
SPU
Software Power Up.
Used in TE mode only.
If SQXR:CFS = 1, before activating the ISDN S-interface in TE mode the SPU and
SQXR:IDC bits have to be set to "1" and then cleared again:
After a subsequent CISQ interrupt (C/I code change; ISTA) and reception of the C/I
code "PU" (Power Up indication in TE mode) the reaction of the processor would be:
–
–
to write an Activate Request command as C/I code in the CIX0 register.
to reset the SPU and SQXR:IDC bits and wait for the following CISQ interrupt.
SPM
TLP
Serial Port Timing Mode;
0: Terminal mode; all three channels of the IOM-2 interface are used
application: TE mode
1: Non-terminal mode; the programmed IOM channel (ADF1:CSEL2-0) is used
applications: LT-T, LT-S modes (8 channels structure IOM-2)
Test Loop
When set to 1 the IDP1 and IDP0 lines are internally connected together,
and the times T1 and T2 are reduced (cf. TIMR).
Semiconductor Group
230
INFINEON [ Infineon ]
