Register Description
C1C1, C1C0 Channel 1 Connect
Determines which of the two channels B1 or IC1 is connected to register
C1R and/or B1CR, for monitoring, test-looping and switching data
to/from the processor.
C1R
B1CR
Read
C1C1
C1C0
Read
Write
Application(s)
0
0
1
0
1
0
IC1
IC1
–
–
IC1
B1
B1
B1
B1
B1 monitoring + IC1 monitoring
B1 monitoring + IC1 looping from/to IOM
B1 access from/to S
a constant value in B1 channel to S
B1 looping from S ; transmission of
a variable pattern in B1 channel to S
0; transmission of
0
.
1
1
B1
B1
–
0
0
.
C2C1, C2C0 Channel 2 Connect
Determines which of the two channels B2 or IC2 is connected to register
C2R and/or B2CR, for monitoring, test-looping and switching data
to/from the processor.
C2R
B2CR
Read
C2C1
C2C0
Read
Write
Application(s)
0
0
1
0
1
0
IC2
IC2
–
–
IC2
B2
B2
B2
B2
B2 monitoring + IC2 monitoring
B2 monitoring + IC2 looping from/to IOM
B2 access from/to S ; transmission of
a constant value in B2 channel to S
B2 looping from S ; transmission of
a variable pattern in B2 channel to S
0
0
.
1
1
B2
B2
–
0
0
.
Note: B-channel access is only possible in TE-mode.
4.3.2
Command/Indication Receive 0
CIR0
Read
Address 31
H
Value after reset: 7C
7
H
0
SQC
BAS
CIC0
CIC1
CODR0
SQC
S/Q Channel Change
A change in the received 4-bit S channel (TE or LT-T mode) or Q channel (NT or LT-S
mode) has been detected. The new code can be read from the SQRR. This bit is reset
by a read of the SQRR.
Semiconductor Group
231
INFINEON [ Infineon ]
