Register Description
BAS
Bus Access Status
Indicates the state of the TIC-bus:
0: the ISAC-S itself occupies the D and C/I channel
1: another device occupies the D and C/I channel
CODR0 C/I Code 0 Receive
Value of the received Command/Indication code. A C/I code is loaded in CODR0 only
after being the same in two consecutive IOM frames and the previous code has been
read from CIR0.
(refer to chapter 3.3.2)
CIC0
CIC1
C/I Code 0 Change
A change in the received Command/Indication code has been recognized. This bit is
set only when a new code is detected in two consecutive IOM frames. It is reset by a
read of CIR0.
C/I Code 1 Change
A change in the received Command/Indication code in IOM channel 1 has been re-
cognized. This bit is set when a new code is detected in one IOM frame. It is reset by
a read of CIR0.
CIC1 is only used if terminal mode is selected.
Note: The BAS and CODR0 bits are updated every time a new C/I code is detected in two
consecutive IOM frames.
If several consecutive valid new codes are detected and CIR0 is not read, only the
first and the last C/I code (and BAS bit) is made available in CIR0 at the first and se-
cond read of that register, respectively.
4.3.3
Command/Indication Transmit 0
CIX0
Write
Address 31
H
Value after reset: 3F
H
7
0
RSS
BAC
1
1
CODX0
RSS
Reset Source Select
Only valid if the terminal specific functions are activated (STCR:TSF).
0:
Subscriber or Exchange Awake
As reset source serves:
– a falling edge on the EAW line (External Subscriber Awake)
– a C/I code change (Exchange Awake).
A logical zero on the EAW line activates also the IOM-interface clock and frame
signal, just as the SPU-bit (SPCR) does.
Semiconductor Group
232
INFINEON [ Infineon ]
