Register Description
4.2.14 B2 Channel Register
B2CR
Read
Address 38
H
7
0
Contains the value received in the B2 channel, as programmed
(see C2C1, C2C0, SPCR register).
4.2.15 Additional Feature Register 1
ADF1
Write
Address 38
H
Value after reset: 00
H
7
0
WTC1 WTC2 TEM
PFS
CFS
FC2
FC1
ITF
WTC1, 2 Watchdog Timer Control 1, 2
After the watchdog timer mode has been selected (STCR:TSF = CIXR:RSS = 1) the
watchdog timer is started.
During every time period of 128 ms the processor has to program the WTC1- and
WTC2-bit in the following sequence:
WTC1
WTC2
1.
2.
1
0
0
1
to reset and restart the watchdog timer.
If not, the timer expires and a WOV interrupt (EXIR) together with a reset pulse is ge-
nerated.
TEM
PFS
Test Mode
In Test mode (TEM = 1, PFS = 0) all layer-1 functions are disabled and the ISAC-S
behaves like an ICC (PEB 2070) device.
Prefilter Select
These bits together determine the pre-filter delay compensation and the test mode
(layer 1 disabled) of the ISAC-S, as follows:
TEM
PFS
Effect
0
0
1
1
0
1
1
0
No pre-filter (0 delay)
Pre-filter delay compensation 520 ns
Pre-filter delay compensation 910 ns
Test mode (layer 1 disabled)
Semiconductor Group
226
INFINEON [ Infineon ]
