Register Description
CFS
Configuration Select
This bit determines clock relations and recovery on S/T and IOM interfaces.
TE Mode:
0: The IOM interface clock and frame signals are always active, "Power Down"
state included.
The states "Power Down" and "Power Up" are thus functionally identical
except for the indication: PD = 1111 and PU = 0111.
With the C/I command Timing (TIM) the processor can enforce the "Power Up"
state.
With C/I command Deactivation Indication (DIU) the "Power Down" state is
reached again.
However, it is also possible to activate the S-interface directly with the C/I
command Activate Request (AR 8/10/L) without the TIM command.
1: The IOM interface clock and frame signals are normally inactive ("Power
Down").
For activating the S-interface the "Power Up" state can be induced by
software (SPU-bit in SPCR register).
After that the S-interface can be activated with the C/I command Activate
Request (AR 8/10/L).
The "Power Down" state can be reached again with the C/I command Deacti-
vation Indication (DIU).
Note:
After reset the IOM interface is always active. To reach the "Power Down"
state the CFS-bit has to be set.
NT, LT-S Modes:
0: In point-to-point configurations (S bus) the bit and frame clock are recovered
from the received bit stream on the S-interface with the internal PLL.
This is to tolerate a variable bit shift of 2 to 8 bit times between the transmitted
and the received frame (max distance of 1.0 ... 1.5 km).
1: In bus configurations only a fixed bit shift of 2-bit times is accepted
according to CCITT (distances up to 150 m).
LT-T Mode:
0: CFS has to be set to "0" always.
Semiconductor Group
227
INFINEON [ Infineon ]
