Register Description
FC2,1 FSC1,2 Control (TE mode only)
Determine the polarity of the symmetrical 8-kHz strobe signals FSC2 and FSC1, re-
spectively:
0: high during the first half of the 125-µs frame (IOM, SLD, SSI), low during the se-
cond half.
1: low during the first half, high during the second half.
Inter-Frame Time Fill
ITF
Selects the inter-frame time fill signal which is transmitted between HDLC frames.
0: idle (continuous 1 s).
1: flags (sequence of patterns: "0111 1110")
Note: In TE and LT-T applications with D-channel access handling (collision resolution), the
only possible inter-frame time fill signal is idle (continuous 1 s). Otherwise the D
channel on the S/T bus cannot be accessed.
4.2.16 Additional Feature Register 2
ADF2
Read/Write Address 39
H
Value after reset: 00
H
7
0
IMS
0
0
0
0
0
0
0
IMS
IOM Mode Selection
IOM-1 interface mode is selected when IMS = 0.
4.2.17 S, Q Channel Receive Register
SQRR
Read
Address 3B
H
Value after reset: 0X
H
7
0
0
0
0
SYN SQR1 SQR2 SQR3 SQR4
SYN
Synchronization State. Used in TE/LT-T mode only (pin M1 = 0).
The S/T receiver has synchronized to the received F and M bits (1) or not (0).
A
SQR1-4 Received S/Q Bits
TE/LT-T mode (pin M1 = 0): Received S bits in frames 1, 6, 11 and 16,
respectively.
LT-S/NT mode (pin M1 = 1): Received F bits in frames 1, 6, 11 and 16,
A
respectively.
Semiconductor Group
228
INFINEON [ Infineon ]
