AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
CPE
6
rw
Command of Parity Error Response
0B
, disable parity error response. AN985B/BX will ignore any
detected parity error and keep on its operating. Default value is 0.
, enable parity error response. AN985B/BX will assert system error
(bit 13 of CSR5) when a parity error is detected.
1B
Res
CMO
5:3
2
ro
rw
Reserved
Command of Master Operation Ability
0B
1B
, disable the bus master ability
, enable the CARDBUS bus master ability. Default value is 1 for
normal operation.
CMSA
CIOSA
1
0
rw
rw
Command of Memory Space Access
0B
1B
, disable the memory space access ability
, enable the memory space access ability
Command of I/O Space Access
0B
1B
, disable the I/O space access ability
, enable the I/O space access ability
Class Code and Revision Number
CC_CR2
Offset
08H
Reset Value
0200 ????H
Class Code and Revision Number
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
%&&
6&
5HV
UR
51
UR
61
UR
UR
UR
Field
Bits
Type
Description
BCC
31:24
ro
Base Class Code
It means AN985B/BX is network controller.
SC
23:16
ro
Subclass Code
It means AN985B/BX is a Fast Ethernet Controller.
Res
RN
15:8
7:4
ro
ro
Reserved
Revision Number
Identifies the revision number of AN985B/BX.
SN
3:0
ro
Step Number
Identifies the AN985B/BX steps within the current revision.
Latency Timer
LT_CR3
Latency Timer
Offset
0CH
Reset Value
0000 0000H
Data Sheet
38
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
