AN985B/BX
Registers and Descriptors Description
CSD_CR1
Configuration Command and Status
Offset
04H
Reset Value
0290 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
5HV
UR
ꢀ ꢃ ꢁ ꢂ
63 6(60 67 5H
6' 6)
35%%
&6 5H &3
&0&0 &,
2 6$ 2ꢀ
6'67
5HV 1&
5HV
UR
(
6 $ $
V
( V (
UZ UZ UZ UZ UR UR UZ UR UR UR
UZ UR UZ
UZ UZ UZ
Field
SPE
Bits
31
Type
rw
Description
Status of Parity Error
1B
, means that AN985B/BX detected a parity error. This bit will be set
in this condition even if the parity error response (bit 6 of CR1) is
disabled.
SES
SMA
30
29
rw
rw
Status of System Error
1B
, means that AN985B/BX asserted the system error pin
Status of Master Abort
1B
, means that AN985B/BX received a master abort and terminated
a master transaction
Status of Target Abort
1B , means that AN985B/BX received a target abort and terminated a
master transaction
STA
28
rw
Res
SDST
27
26:25
ro
ro
Reserved
Status of Device Select Timing
The timing of the assertion of device select.
01B , means a medium assertion of DEVSEL#
SDPR
24
rw
Status of Data Parity Report
1: when three conditions are met:
AN985B/BX asserted parity error - PERR# or it detected parity error
asserted by other device.
AN985B/BX is operating as a bus master.
5AN985B/BX’s parity error response bit (bit 6 of CR1) is enabled.
SFBB
23
ro
Status of Fast Back-to-Back
Always 1, since AN985B/BX has the ability to accept fast back-to-back
transactions.
Res
NC
22:21
20
ro
ro
Reserved
New Capabilities
This bit indicates that whether the AN985B/BX provides a list of extended
capabilities, such as CARDBUS power management.
0B
1B
, the AN985B/BX doesn’t provide New Capabilities
, the AN985B/BX provides the CARDBUS management function
Res
CSE
19:9
8
ro
rw
Reserved
Command of System Error Response
1B
, enable system error response. AN985B/BX will assert SERR#
when it find a parity error on the address phase.
Res
7
ro
Reserved
Data Sheet
37
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
