AN985B/BX
Registers and Descriptors Description
Table 9
Mode
Registers Access Types (cont’d)
Symbol Description Hardware (HW)
rwv
Description Software (SW)
Read only
ro
Register is set by HW (register between SW can only read this register
input and output -> one cycle delay)
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Latch high,
self clearing
Latch low,
self clearing
lhsc
llsc
Latch high signal at high level, clear on SW can read the register
read
Latch high signal at low-level, clear on SW can read the register
read
Latch high,
lhmk
llmk
ihsc
ilsc
Latch high signal at high level, register SW can read the register, with write mask
mask clearing
cleared with written mask
the register can be cleared (1 clears)
Latch low,
mask clearing
Interrupt high,
self clearing
Interrupt low,
self clearing
Latch high signal at low-level, register SW can read the register, with write mask
cleared on read
Differentiate the input signal (low-
>high) register cleared on read
the register can be cleared (1 clears)
SW can read the register
Differentiate the input signal (high-
>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
Interrupt low,
mask clearing
ihmk
ilmk
Differentiate the input signal (high-
SW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Differentiate the input signal (low-
>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable ien
register
latch_on_reset lor
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
SW can read and write this register
Register is read and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the hw, the Writing to the register generates a strobe
register will be cleared due to a HW
mechanism.
signal for the HW (1 pdi clock cycle)
Register is read and writable by SW.
Table 10
Registers Clock Domains
Clock Short Name
Description
8.1.1
AN985B/BX Configuration Registers Descriptions
Offset
00h
04h
b31------------------------------------------------b16 b15------------------------------------------------------------b0
Device ID*
Status
Base Class Code Subclass
Vendor ID*
Command
-----------
08h
Revision# Step#
Data Sheet
35
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
