IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Truth Table I: Random Access Read and Write(1,2)
Inputs/Outputs
R/W
H
H
H
L
I/O
0
-I/O
7
I/O8-I/O15
Mode
CE
L
CMD
H
OE
L
LB
L
UB
L
DATAOUT
DATAOUT
High-Z
DATAIN
DATAIN
High-Z
DATAOUT Read both Bytes.
L
H
L
L
H
L
High-Z
Read lower Byte only.
L
H
L
H
L
DATAOUT Read upper Byte only.
(3)
L
H
H
L
DATAIN
High-Z
DATAIN
High-Z
High-Z
High-Z
DATAIN
DATAOUT
Write to both Bytes.
(3)
L
H
L
H
L
H
L
Write to lower Byte only.
Write to upper Byte only.
(3)
L
H
L
H
X
H
X
H
X
X
H
H
L
H
X
H
X
L
X
X
H
High-Z
Both Bytes deselected and powered down.
Outputs disabled but not powered down.
Both Bytes deselected but not powered down.
H
High-Z
L
H
High-Z
(3)
(4)
(4)
H
H
L
H
L
L
L
DATAIN
DATAOUT
Write I/O
0-I/O11 to the Buffer Command Register.
(4)
(4)
L
L
L
H
Read contents of the Buffer Command Register
via I/O -I/O12.
0
3016 tbl 11
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2. RST, SCE, CNTEN, SR/W, SLD, SSTRT1, SSTRT2, SCLK, SI/O0-SI/O15, EOB1, EOB2, and SOE are unrelated to the random access port control and operation.
3. If OE = VIL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven.
4. Byte operations to control register using UB and LB separately are also allowed.
Truth Table II: Sequential Read(1,2,3,6,8)
Inputs/Outputs
SCLK
SR/W
H
SI/O
[EOB
[EOB1 - 1
[EOB
[EOB2 - 1
High-Z
MODE
Counter Advanced Sequential Read with EOB
Non-Counter Advanced Sequential Read, without EOB
Counter Advanced Sequential Read with EOB reched.
Non-Counter Advanced Sequential Read without EOB
Counter Advanced Sequential Non-Read with EOB
SCE
L
CNTEN
EOB
1
EOB
2
SOE
L
L
H
L
H
L
LOW LAST
LAST LAST
1
]
1 reached.
↑
↑
↑
↑
↑
L
H
L
]
1
reached
L
H
LAST
LAST LAST
LOW LOW
LOW
L
2]
2
L
H
L
]
2
reached.
L
H
H
1
and EOB2 reached.
3016 tbl 12
Truth Table III: Sequential Write(1,2,3,4,5,6,7,8)
Inputs/Outputs
SCLK
SR/W
L
SI/O
SI/OIN Non-Counter Advanced Sequential Write, without EOB
SI/OIN Coounter Advanced Sequential Write with EOB and EOB
MODE
SCE CNTEN
EOB
LAST LAST
LOW LOW
1
EOB
2
SOE
H
L
L
H
L
H
L
1
or EOB
2 reached.
↑
L
H
1
2
reached.
↑
H
H
X
LAST LAST
NEXT NEXT
X
High-Z No Write or Read due to Sequential port Deselect. No counter advance.
High-Z No Write or Read due to Sequential port Deselect. Counter does advance.
↑
↑
X
X
3016 tbl 13
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance. LOW = VOL.
2. RST, SLD, SSTRT1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations.
3. CE, OE, R/W, CMD, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently with the sequential
port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. SOE must be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising edge of the clock
during the cycle in which SR/W = VIL.
5. SI/OIN refers to SI/O0-SI/O15 inputs.
6. "LAST" refers to the previous value still being output, no change.
7. Termination of a write is done on the LOW-to-HIGH transition of SCLK if SR/W or SCE is HIGH.
8. When CLKEN=LOW, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter Enable Cycle after
Reset, Read (and write) Cycle".
6.42
7
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
