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IBM3009K2672 参数 Datasheet PDF下载

IBM3009K2672图片预览
型号: IBM3009K2672
PDF下载: 下载PDF文件 查看货源
内容描述: [Framer, CMOS, CBGA474, CERAMIC, BGA-474]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 287 页 / 4239 K
品牌: IBM [ IBM ]
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IBM3009K2672  
IBM SONET/SDH Framer  
Expansion Interface Pin Descriptions  
Pin Name  
Pin No.  
I/O  
Type  
Pin Description  
Expansion Interface Control: Control pin for Expansion interface. This pin  
is used for STM-16/STS-48 operation.  
TXEXPIN  
R09  
I
LVTTL-5sd  
Expansion Interface Control: Control pin for Expansion interface. This pin  
is used for STM-16/STS-48 operation.  
TXEXPOUT  
RXEXPIN  
R11  
T12  
U13  
T13  
T14  
O
I
LVTTL-5sd  
LVTTL-5sd  
LVTTL-5sd  
LVTTL-5sd  
LVTTL-5fd  
Expansion Interface Control: Control pin for Expansion interface. This pin  
is used for STM-16/STS-48 operation.  
Expansion Interface Control: Control pin for Expansion interface. This pin  
is used for STM-16/STS-48 operation.  
RXEXPOUT  
TXFRMIN  
O
I
Expansion Interface Control: Control pin for Expansion interface. This pin  
is used for STM-16/STS-48 operation.  
Expansion Interface Control: Control pin for Expansion interface. This pin  
is used for STM-16/STS-48 operation.  
TXFRMOUT  
O
Ring Port Interface Pin Descriptions  
Pin Name  
Pin No.  
I/O  
Type  
Pin Description  
Transmit Ring Port Clock Input: This signal is connected to the RXRING-  
LVTTL-5sd CLK output of a mating SONET/SDH framer. TXRINGD is clocked into the  
SONET/SDH framer on the rising edge of this 19.44 MHz clock.  
TXRINGCLK  
V13  
I
Transmit Ring Port Data Input: A serial input that is connected to a mating  
SONET/SDH framer’s RXRINGD signal to allow communication of the  
debounced K1, K2 and K3 bytes, Path REI and 3-Bit Path RDI, Line RDI  
LVTTL-5sd and Line REI, New K3 Indication, and New APS Indication for all four  
STM-1/STS-3cs or STM-4c/STS-12c to facilitate Ring mode operation. The  
data on this pin is clocked into the SONET/SDH framer on the rising edge of  
the TXRINGCLK signal.  
TXRINGD  
RXRINGCLK  
RXRINGD  
V12  
V15  
V14  
I
Receive Ring Port Clock Output: RXRINGD is output on the falling edge  
LVTTL-5sd of this 19.44 MHz clock, which is derived from the Transmit Line Reference  
Clock.  
O
O
Receive Ring Port Data Output: A serial output that provides the  
debounced K1, K2, and K3 bytes, Path REI and 3-Bit Path RDI, Line RDI  
and Line REI, New K3 Indication, and New APS Indication for all four  
LVTTL-5sd STM-1/STS-3cs or STM-4c/STS-12c to facilitate Ring mode operation. A  
start sequence and an address field is used to delineate the information  
contained on this signal output. RXRINGD is output on the falling edge of  
RXRINGCLK.  
ssframer.01  
8/27/99  
Pin Information  
Page 47 of 279  
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