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IBM3009K2672 参数 Datasheet PDF下载

IBM3009K2672图片预览
型号: IBM3009K2672
PDF下载: 下载PDF文件 查看货源
内容描述: [Framer, CMOS, CBGA474, CERAMIC, BGA-474]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 287 页 / 4239 K
品牌: IBM [ IBM ]
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IBM3009K2672  
IBM SONET/SDH Framer  
APS Interface Pin Descriptions  
Pin Name  
Pin No.  
I/O  
Type  
Pin Description  
TXAPSDAT(8)  
TXAPSDAT(7)  
TXAPSDAT(6)  
TXAPSDAT(5)  
TXAPSDAT(4)  
TXAPSDAT(3)  
TXAPSDAT(2)  
TXAPSDAT(1)  
TXAPSDAT(0)  
R13  
R15  
P12  
P13  
P14  
N11  
N13  
N15  
M12  
I/O (T)  
I/O (T)  
I/O (T)  
I/O (T)  
I/O (T)  
I/O (T)  
I/O (T)  
I/O (T)  
I/O (T)  
Transmit APS Data: Bit 0 is the LSB. This is a bidirectional port. When the  
SONET/SDH framer is configured to output data on the transmit APS inter-  
face, these pins are outputs. When the SONET/SDH framer is configured to  
accept data from the transmit APS interface, these pins are inputs. This  
data bus is used to pass transmit C-4 (VC-4) data from one SONET/SDH  
framer to another.  
LVTTL-5sd  
Transmit APS Parity: This is a bidirectional pin. When the SONET/SDH  
framer is configured to output data on the transmit APS interface, this pin is  
an output and provides parity for the TXAPSDAT(8:0) bus. When the  
SONET/SDH framer is configured to accept data from the transmit APS  
interface, this pin is an input and accepts parity from the SONET/SDH  
framer that is driving the transmit APS interface.  
TXAPSPAR  
M13  
I/O (T)  
LVTTL-5sd  
Transmit APS Provided Data Valid: This is a bidirectional pin. When the  
SONET/SDH framer is configured to output data on the transmit APS inter-  
face, this pin is an output and indicates when data on the TXAPSDAT(8:0)  
bus is valid. A high means that data is valid on the considered clock edge. A  
TXAPSDAVA  
M14  
I/O (T)  
LVTTL-5sd low means that data is not valid. When the SONET/SDH framer is config-  
ured to accept data from the transmit APS interface, this pin is an input and  
tells the SONET/SDH framer if the data being received on the TXAPS-  
DAT(8:0) bus is valid or not. A high means that data is valid on the consid-  
ered clock edge. A low means that data is not valid.  
Transmit APS Data Request: This is a bidirectional pin. When the  
SONET/SDH framer is configured to output data on the Transmit APS inter-  
face, this pin is an input and tells the SONET/SDH framer that one of the  
other connected SONET/SDH framers is requesting data. A high means  
LVTTL-5sd that data is being requested. A low means that no data is requested. When  
the SONET/SDH framer is configured to accept data from the transmit APS  
interface, this pin is an output and indicates that this SONET/SDH framer is  
requesting data. A high means that data is being requested. A low means  
that no data is requested.  
TXAPSDARQ  
L11  
I/O (T)  
RXAPSDAT(8)  
RXAPSDAT(7)  
RXAPSDAT(6)  
RXAPSDAT(5)  
RXAPSDAT(4)  
RXAPSDAT(3)  
RXAPSDAT(2)  
RXAPSDAT(1)  
RXAPSDAT(0)  
L13  
L15  
K11  
K12  
K13  
K14  
J13  
J15  
H14  
I/O (T)  
I/O (T)  
I/O (T)  
I/O (T)  
I/O (T)  
I/O (T)  
I/O (T)  
I/O (T)  
I/O (T)  
Receive APS Data: Bit 0 is the LSB. This is a bidirectional port. When the  
SONET/SDH framer is configured to output data on the receive APS inter-  
face, these pins are outputs. When the SONET/SDH framer is configured to  
accept data from the receive APS interface, these pins are inputs. This data  
bus is used to pass receive C-4 (VC-4) data from one SONET/SDH framer  
to another.  
LVTTL-5sd  
Receive APS Parity: This is a bidirectional pin. When the SONET/SDH  
framer is configured to output data on the receive APS interface, this pin is  
an output and provides parity for the RXAPSDAT(8:0) bus. When the  
SONET/SDH framer is configured to accept data from the receive APS  
RXAPSPAR  
H15  
I/O (T)  
LVTTL-5sd  
interface, this pin is an input and accepts parity from the SONET/SDH  
framer that is driving the receive APS interface.  
Receive APS Provided Data Valid: This is a bidirectional pin. When the  
SONET/SDH framer is configured to output data on the receive APS inter-  
face, this pin is an output and indicates when data on the RXAPSDAT(8:0)  
bus is valid. A high means that data is valid on the considered clock edge. A  
LVTTL-5sd low means that data is not valid. When the SONET/SDH framer is config-  
ured to accept data from the receive APS interface, this pin is an input and  
tells the SONET/SDH framer if the data being received on the RXAPS-  
DAT(8:0) bus is valid or not. A high means that data is valid on the consid-  
ered clock edge. A low means that data is not valid.  
RXAPSDAVA  
G15  
I/O (T)  
Pin Information  
ssframer.01  
8/27/99  
Page 46 of 279  
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