IBM3009K2672
IBM SONET/SDH Framer
GPP Interface Pin Descriptions (Sheet 1 of 2)
Pin Name
Pin No.
I/O
Type
Pin Description
GPP Clock:
Clock for the GPP interface in the SONET/SDH framer. This clock is
always required, regardless of whether an asynchronous or synchronous
interface is selected via the INTFMODE pin. When an asynchronous type
interface is selected, this clock can have a maximum frequency of 50 MHz.
When a synchronous interface is selected, this clock can have a maximum
frequency of 33.3 MHz. All signals are transferred on the falling edge of
this clock when the synchronous interface is selected. The lowest fre-
quency that this clock can have is either 10 MHz or the frequency of the
microprocessor clock, whichever is higher.
GPPCLK
AE11
I
LVTTL-5sp
GPDATA(7)
GPDATA(6)
GPDATA(5)
GPDATA(4)
GPDATA(3)
GPDATA(2)
GPDATA(1)
GPDATA(0)
AE17
AD17
AC17
AB17
AE18
AD18
AC18
AB18
GPP Data: (True)
I/O (T)
LVTTL-5f
Bidirectional bus for data to/from the SONET/SDH framer GPP interface.
Bit 0 is the LSB.
GPADDR(13)
GPADDR(12)
GPADDR(11)
GPADDR(10)
GPADDR(9)
GPADDR(8)
GPADDR(7)
GPADDR(6)
GPADDR(5)
GPADDR(4)
GPADDR(3)
GPADDR(2)
GPADDR(1)
GPADDR(0)
Y13
AE14
AC14
AB14
Y14
AD15
AB15
AA15
Y15
AE16
AD16
AB16
AA16
Y16
GPP Address:
I
LVTTL-5s
The 14-bit address of the register or GRA location within the SONET/SDH
framer that is to be read or written. Bit 0 is the LSB.
GPP Read/Write [R/W] (Motorola Mode) or Write [WR] (Intel Mode):
Data transfer control signal.
Motorola Mode: This signal is high during a data read operation and
low for a data write operation. A low enables data from the
GPDATA(7:0) bus to be written into the addressed location. A high
enables data to be read from the addressed location.
GPR/W, GPWR
AE12
I
LVTTL-5sp
Intel Mode: This signal is high during a data read operation and low
for a data write operation. A low enables data from the GPDATA(7:0)
bus to be written into the addressed location.
GPP Data Strobe [DS] (Motorola Mode) or Read [RD] (Intel Mode):
(Active low)
Motorola Mode: When asserted low during a read cycle, this signal
indicates that the SONET/SDH framer is to put data out on the
GPDATA(7:0) bus. When asserted low during a write cycle, this sig-
nal tells the SONET/SDH framer that there is valid data on the
GPDATA(7:0) bus.
GPDS, GPRD
AD13
I
LVTTL-5sp
Intel Mode: This signal is high during a data write operation and low
during a data read operation. A low enables data to be read from the
addressed location.
Pin Information
Page 42 of 279
ssframer.01
8/27/99
IBM [ IBM ]
