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IBM3009K2672 参数 Datasheet PDF下载

IBM3009K2672图片预览
型号: IBM3009K2672
PDF下载: 下载PDF文件 查看货源
内容描述: [Framer, CMOS, CBGA474, CERAMIC, BGA-474]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 287 页 / 4239 K
品牌: IBM [ IBM ]
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IBM3009K2672  
IBM SONET/SDH Framer  
Telecom Bus Interface Pin Descriptions (Sheet 3 of 6)  
Pin Name  
Pin No.  
I/O  
Type  
Pin Description1  
Telecom Bus 3 Transmit Input Synchronous Payload Envelope Signal:  
This signal is high for the SPE bytes and low for the TOH bytes on Telecom  
Bus 3. If transmit retiming is turned off and no J1 pulse is present in  
TXTB3C1J1, this pin can be tied low.  
TXTB3SPE  
K06  
I
LVTTL-5sd  
Telecom Bus 3 Transmit Input Parity:  
Parity for the signals of Telecom Bus 3. It should be calculated by the trans-  
mitting device according to the settings of the PFULL3, PEVEN3, and  
PENA3 control bits in the SONET/SDH framer. Parity errors are reported  
via the TB3PAR alarm bit, but no actions are taken.  
TXTB3PAR  
TXTB3FAIL  
K07  
J01  
I
I
LVTTL-5sp  
LVTTL-5sp  
Telecom Bus 3 Transmit Input Failure Indication:  
TXTB3FAIL indicates that a failure has occurred on the device transmitting  
on Telecom Bus 3. When TXTB3FAIL goes high, AIS-P is transmitted on  
STM-1 #3/STS-3c #3.  
TXTB4DATA(7)  
TXTB4DATA(6)  
TXTB4DATA(5)  
TXTB4DATA(4)  
TXTB4DATA(3)  
TXTB4DATA(2)  
TXTB4DATA(1)  
TXTB4DATA(0)  
M06  
M07  
M08  
L01  
L02  
L03  
L05  
L07  
Telecom Bus 4 Transmit Input Data:  
19.44 Mbytes/s AU-4 (transmit retiming turned off) or VC-4 (transmit retim-  
ing turned on) data input on these pins is inserted into the outgoing STM-1  
#4. This data is clocked into the SONET/SDH framer on the rising edge of  
TXTB4CLK. Bit 7 is the MSB and is transmitted first.  
I
LVTTL-5sp  
Telecom Bus 4 Transmit Input Clock:  
All of the signals for Telecom Bus 4 are clocked into the SONET/SDH  
framer on the rising edge of this 19.44 MHz clock. TXTB4CLK must be fre-  
quency locked to either TXCCLK or TXCCLK if transmit retiming is not per-  
formed.  
TXTB4CLK  
TXTB4C1J1  
N03  
N05  
I
I
LVTTL-5sp  
LVTTL-5sd  
Telecom Bus 4 Transmit Input Slot Indication:  
When the TXTB4SPE signal is high, TXTB4C1J1 indicates the position of  
the J1 byte. When the TXTB4SPE signal is low, TXTB4C1J1 indicates the  
position of the C1 byte. The J1 and C1 pulses are required if transmit retim-  
ing is turned on. If transmit retiming is turned off, this signal becomes a slot  
identifier.  
Telecom Bus 4 Transmit Input Synchronous Payload Envelope Signal:  
This signal is high for the SPE bytes and low for the TOH bytes on Telecom  
Bus 4. If transmit retiming is turned off and no J1 pulse is present in  
TXTB4C1J1, this pin can be tied low.  
TXTB4SPE  
TXTB4PAR  
TXTB4FAIL  
N07  
M02  
M04  
I
I
I
LVTTL-5sd  
LVTTL-5sp  
LVTTL-5sp  
Telecom Bus 4 Transmit Input Parity:  
Parity for the signals of Telecom Bus 4. It should be calculated by the trans-  
mitting device according to the settings of the PFULL4, PEVEN4, and  
PENA4 control bits in the SONET/SDH framer. Parity errors are reported  
via the TB4PAR alarm bit, but no actions are taken.  
Telecom Bus 4 Transmit Input Failure Indication:  
TXTB4FAIL indicates that a failure has occurred on the device transmitting  
on Telecom Bus 4. When TXTB4FAIL goes high, AIS-P is transmitted on  
STM-1 #4/STS-3c #4.  
RXCCLK  
RXCFRM  
W07  
T08  
I
I
No Connect: Leave unconnected.  
No Connect: Leave unconnected.  
1. When STM-4c or STS-12c frames are processed, the four transmit and four receive Telecom Buses operate in parallel as two 32-  
bit wide Telecom Buses.  
Pin Information  
ssframer.01  
8/27/99  
Page 38 of 279  
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