IBM3009K2672
IBM SONET/SDH Framer
Telecom Bus Interface Pin Descriptions (Sheet 5 of 6)
Pin Name
Pin No.
I/O
Type
Pin Description1
Telecom Bus 2 Receive C1J1 Signal:
When the control bit C2POS is set to ‘1’, this signal identifies the first C1
byte in the RXTB2DATA(7:0) stream when RXTB2C1J1 is high and
RXTB2SPE is low, while the J1 byte in RXTB2DATA(7:0) is identified when
RXTB2C1J1 and RXTB2SPE are high. When C2POS is set to ’0’,
RXTB2C1J1 goes high only during the last A2 byte time of
RXTB2DATA(7:0).
RXTB2C1J1
V07
O (T)
LVTTL-5s
Telecom Bus 2 Receive SPE Signal:
RXTB2SPE is high during the SPE bytes of RXTB2DATA(7:0). If a pointer
decrement occurs, RXTB2SPE will go high coincident with the three H3
bytes in RXTB2DATA(7:0). If a pointer increment occurs, RXTB2SPE will
go low coincident with the three SPE bytes immediately after the H3 bytes
of the RXTB2DATA(7:0) stream.
RXTB2SPE
RXTB2PAR
W01
W02
O (T)
O (T)
LVTTL-5s
LVTTL-5s
Telecom Bus 2 Receive Parity Signal:
Parity for the receive signals of Telecom Bus 2. It is calculated by the
SONET/SDH framer according to the settings of the PFULL2, PEVEN2,
and PENA2 control bits.
Telecom Bus 2 Receive Failure Indication:
RXTB2FAIL goes high when the SONET/SDH framer detects errors that
would cause an AIS-P to be generated in the receive STM-1 #2/STS-3c #2
signal. These alarms are: Loss of Pointer, or Path AIS, or Line AIS detected
in STM-1 #2/STS-3c #2, or Loss of Clock or Loss of Data detected at the
SONET/SDH framer’s receive inputs. RXTB2FAIL will stay active as long
as the failure condition exists.
RXTB2FAIL
W03
O (T)
LVTTL-5s
LVTTL-5s
RXTB3DATA(7)
RXTB3DATA(6)
RXTB3DATA(5)
RXTB3DATA(4)
RXTB3DATA(3)
RXTB3DATA(2)
RXTB3DATA(1)
RXTB3DATA(0)
W05
Y01
Y02
Y03
Y04
Y05
AA01
AA03
Telecom Bus 3 Receive Data:
SPE and TOH data from STM-1 #3/STS-3c #3 are output on these pins. Bit
7 is the MSB and was received first. Bit 0 is the LSB and was received last.
All TOH and SPE data are passed out of the SONET/SDH framer and are
not modified. The data on these pins is clocked out of the SONET/SDH
framer on either the rising or falling edge of RXTB3CLK depending on the
setting of the CKINV3 control bit.
O (T)
Telecom Bus 3 Receive Clock:
All Telecom Bus 3 receive signals are clocked out of the SONET/SDH
framer on the falling edge of RXTB3CLK when the CKINV3 control bit is set
to ’0’. If CKINV3 is set to ‘1’, the Telecom Bus 3 receive signals are clocked
out on the rising edge of RXTB3CLK. This clock is 19.44 MHz.
RXTB3CLK
AB01
AB02
O (T)
O (T)
LVTTL-5s
LVTTL-5s
Telecom Bus 3 Receive C1J1 Signal:
When the control bit C3POS is set to ‘1’, this signal identifies the first C1
byte in the RXTB3DATA(7:0) stream when RXTB3C1J1 is high and
RXTB3SPE is low, while the J1 byte in RXTB3DATA(7:0) is identified when
RXTB3C1J1 and RXTB3SPE are high. When C3POS is set to ’0’,
RXTB3C1J1 goes high only during the last A2 byte time of
RXTB3DATA(7:0).
RXTB3C1J1
Telecom Bus 3 Receive SPE Signal:
RXTB3SPE is high during the SPE bytes of RXTB3DATA(7:0). If a pointer
decrement occurs, RXTB3SPE will go high coincident with the three H3
bytes in RXTB3DATA(7:0). If a pointer increment occurs, RXTB3SPE will
go low coincident with the three SPE bytes immediately after the H3 bytes
of the RXTB3DATA(7:0) stream.
RXTB3SPE
AB03
O (T)
LVTTL-5s
1. When STM-4c or STS-12c frames are processed, the four transmit and four receive Telecom Buses operate in parallel as two 32-
bit wide Telecom Buses.
Pin Information
ssframer.01
8/27/99
Page 40 of 279
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