IBM3009K2672
IBM SONET/SDH Framer
Telecom Bus Interface Pin Descriptions (Sheet 4 of 6)
Pin Name
Pin No.
I/O
Type
Pin Description1
RXTB1DATA(7)
RXTB1DATA(6)
RXTB1DATA(5)
RXTB1DATA(4)
RXTB1DATA(3)
RXTB1DATA(2)
RXTB1DATA(1)
RXTB1DATA(0)
P02
P04
P06
P07
P08
R01
R02
R03
Telecom Bus 1 Receive Data:
SPE and TOH data from STM-1 #1/STS-3c #1 are output on these pins. Bit
7 is the MSB and was received first. Bit 0 is the LSB and was received last.
All TOH and SPE data are passed out of the SONET/SDH framer and are
not modified. The data on these pins is clocked out of the SONET/SDH
framer on either the rising or falling edge of RXTB1CLK depending on the
setting of the CKINV1 control bit.
O (T)
LVTTL-5s
Telecom Bus 1 Receive Clock:
All Telecom Bus 1 receive signals are clocked out of the SONET/SDH
framer on the falling edge of RXTB1CLK when the CKINV1 control bit is set
to ’0’. If CKINV1 is set to ‘1’, the Telecom Bus 1 receive signals are clocked
out on the rising edge of RXTB1CLK. This clock is 19.44 MHz.
RXTB1CLK
R05
O (T)
O (T)
LVTTL-5s
LVTTL-5s
Telecom Bus 1 Receive C1J1 Signal:
When the control bit C1POS is set to ‘1’, this signal identifies the first C1
byte in the RXTB1DATA(7:0) stream when RXTB1C1J1 is high and
RXTB1SPE is low, while the J1 byte in the RXTB1DATA(7:0) stream is
identified when RXTB1C1J1 and RXTB1SPE are high. When C1POS is set
to ’0’, RXTB1C1J1 goes high only during the last A2 byte time of the
RXTB1DATA(7:0) signal.
RXTB1C1J1
R07
Telecom Bus 1 Receive SPE Signal:
RXTB1SPE is high during the SPE bytes of RXTB1DATA(7:0). If a pointer
decrement occurs, RXTB1SPE will go high coincident with the three H3
bytes in RXTB1DATA(7:0). If a pointer increment occurs, RXTB1SPE will
go low coincident with the three SPE bytes immediately after the H3 bytes
of the RXTB1DATA(7:0) stream.
RXTB1SPE
RXTB1PAR
T02
T04
O (T)
O (T)
LVTTL-5s
LVTTL-5s
Telecom Bus 1 Receive Parity Signal:
Parity for the receive signals of Telecom Bus 1. It is calculated by the
SONET/SDH framer according to the settings of the PFULL1, PEVEN1,
and PENA1 control bits.
Telecom Bus 1 Receive Failure Indication:
RXTB1FAIL goes high when the SONET/SDH framer detects errors that
would cause an AIS-P to be generated in the receive STM-1 #1/STS-3c #1
signal. These alarms are: Loss of Pointer, or Path AIS, or Line AIS detected
in STM-1 #1/STS-3c #1, or Loss of Clock or Loss of Data detected at the
SONET/SDH framer’s receive inputs. RXTB1FAIL will stay active as long
as the failure condition exists.
RXTB1FAIL
T06
O (T)
LVTTL-5s
RXTB2DATA(7)
RXTB2DATA(6)
RXTB2DATA(5)
RXTB2DATA(4)
RXTB2DATA(3)
RXTB2DATA(2)
RXTB2DATA(1)
RXTB2DATA(0)
T07
U01
U03
U05
U07
V02
V04
V05
Telecom Bus 2 Receive Data:
SPE and TOH data from STM-1 #2/STS-3c #2 are output on these pins. Bit
7 is the MSB and was received first. Bit 0 is the LSB and was received last.
All TOH and SPE data are passed out of the SONET/SDH framer and are
not modified. The data on these pins is clocked out of the SONET/SDH
framer on either the rising or falling edge of RXTB2CLK depending on the
setting of the CKINV2 control bit.
O (T)
O (T)
LVTTL-5s
LVTTL-5s
Telecom Bus 2 Receive Clock:
All Telecom Bus 2 receive signals are clocked out of the SONET/SDH
framer on the falling edge of RXTB2CLK when the CKINV2 control bit is set
to ’0’. If CKINV2 is set to ‘1’, the Telecom Bus 2 receive signals are clocked
out on the rising edge of RXTB2CLK. This clock is 19.44 MHz.
RXTB2CLK
V06
1. When STM-4c or STS-12c frames are processed, the four transmit and four receive Telecom Buses operate in parallel as two 32-
bit wide Telecom Buses.
ssframer.01
8/27/99
Pin Information
Page 39 of 279
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