IBM3009K2672
IBM SONET/SDH Framer
Telecom Bus Interface Pin Descriptions (Sheet 2 of 6)
Pin Name
Pin No.
I/O
Type
Pin Description1
TXTB2DATA(7)
TXTB2DATA(6)
TXTB2DATA(5)
TXTB2DATA(4)
TXTB2DATA(3)
TXTB2DATA(2)
TXTB2DATA(1)
TXTB2DATA(0)
F02
F03
F04
E01
D01
D02
C01
C02
Telecom Bus 2 Transmit Input Data:
19.44 Mbytes/s AU-4 (transmit retiming turned off) or VC-4 (transmit retim-
ing turned on) data input on these pins is inserted into the outgoing STM-1
#2. This data is clocked into the SONET/SDH framer on the rising edge of
TXTB2CLK. Bit 7 is the MSB and is transmitted first.
I
LVTTL-5sp
Telecom Bus 2 Transmit Input Clock:
All of the signals for Telecom Bus 2 are clocked into the SONET/SDH
framer on the rising edge of this 19.44 MHz clock. TXTB2CLK must be fre-
quency locked to either TXCCLK or TXCCLK if transmit retiming is not per-
formed.
TXTB2CLK
TXTB2C1J1
G01
G02
I
I
LVTTL-5sp
LVTTL-5sd
Telecom Bus 2 Transmit Input Slot Indication:
When the TXTB2SPE signal is high, TXTB2C1J1 indicates the position of
the J1 byte. When the TXTB2SPE signal is low, TXTB2C1J1 indicates the
position of the C1 byte. The J1 and C1 pulses are required if transmit retim-
ing is turned on. If transmit retiming is turned off, this signal becomes a slot
identifier.
Telecom Bus 2 Transmit Input Synchronous Payload Envelope Signal:
This signal is high for the SPE bytes and low for the TOH bytes on Telecom
Bus 2. If transmit retiming is turned off and no J1 pulse is present in
TXTB2C1J1, this pin can be tied low.
TXTB2SPE
TXTB2PAR
TXTB2FAIL
G03
G05
F01
I
I
I
LVTTL-5sd
LVTTL-5sp
LVTTL-5sp
Telecom Bus 2 Transmit Input Parity:
Parity for the signals of Telecom Bus 2. It should be calculated by the trans-
mitting device according to the settings of the PFULL2, PEVEN2, and
PENA2 control bits in the SONET/SDH framer. Parity errors are reported
via the TB2PAR alarm bit, but no actions are taken.
Telecom Bus 2 Transmit Input Failure Indication:
TXTB2FAIL indicates that a failure has occurred on the device transmitting
on Telecom Bus 2. When TXTB2FAIL goes high, AIS-P is transmitted on
STM-1 #2/STS-3c #2.
TXTB3DATA(7)
TXTB3DATA(6)
TXTB3DATA(5)
TXTB3DATA(4)
TXTB3DATA(3)
TXTB3DATA(2)
TXTB3DATA(1)
TXTB3DATA(0)
J03
J05
J07
H02
H04
H05
H06
H07
Telecom Bus 3 Transmit Input Data:
19.44 Mbytes/s AU-4 (transmit retiming turned off) or VC-4 (transmit retim-
ing turned on) data input on these pins is inserted into the outgoing STM-1
#3. This data is clocked into the SONET/SDH framer on the rising edge of
TXTB3CLK. Bit 7 is the MSB and is transmitted first.
I
LVTTL-5sp
Telecom Bus 3 Transmit Input Clock:
All of the signals for Telecom Bus 3 are clocked into the SONET/SDH
framer on the rising edge of this 19.44 MHz clock. TXTB1CLK must be fre-
quency locked to either TXCCLK or TXCCLK if transmit retiming is not per-
formed.
TXTB3CLK
TXTB3C1J1
K02
K04
I
I
LVTTL-5sp
LVTTL-5sd
Telecom Bus 3 Transmit Input Slot Indication:
When the TXTB3SPE signal is high, TXTB3C1J1 indicates the position of
the J1 byte. When the TXTB3SPE signal is low, TXTB3C1J1 indicates the
position of the C1 byte. The J1 and C1 pulses are required if transmit retim-
ing is turned on. If transmit retiming is turned off, this signal becomes a slot
identifier.
1. When STM-4c or STS-12c frames are processed, the four transmit and four receive Telecom Buses operate in parallel as two 32-
bit wide Telecom Buses.
ssframer.01
8/27/99
Pin Information
Page 37 of 279
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