IBM3009K2672
IBM SONET/SDH Framer
Telecom Bus Interface Pin Descriptions (Sheet 1 of 6)
Pin Name
Pin No.
I/O
Type
Pin Description1
Transmit Reference Clock:
TXCCLK is provided as a transmit reference timebase for devices con-
nected to the transmit Telecom Bus interface. TXCCLK is configured to be
19.44 MHz for STM-1/STS-3c/STM-4/STS-12/STM-4c/STS-12c operation.
TXCCLK
D05
O
LVTTL-5sp
Transmit Reference Clock Not:
TXCCLK is the complement of TXCCLK and is provided to support devices
that may have different timing requirements for clocking in the TXCFRM
signal. TXCCLK is configured to be 19.44 MHz for STM-1/STS-3c/STM-
4/STS-12/STM-4c/STS-12c operation.
TXCCLK
TXCFRM
E05
F06
O
O
LVTTL-5sp
LVTTL-5sp
Transmit Reference Frame Pulse:
TXCFRM must be used to synchronize the data that is input to the Telecom
Bus ports. This signal is synchronous to TXCCLK.
TXCC1J1
TXCSPE
D06
B05
O
O
No Connect: Leave unconnected.
No Connect: Leave unconnected.
TXTB1DATA(7)
TXTB1DATA(6)
TXTB1DATA(5)
TXTB1DATA(4)
TXTB1DATA(3)
TXTB1DATA(2)
TXTB1DATA(1)
TXTB1DATA(0)
A02
A03
B03
A04
B04
D04
E04
F05
Telecom Bus 1 Transmit Input Data:
19.44 Mbytes/s AU-4 (transmit retiming turned off) or VC-4 (transmit retim-
ing turned on) data input on these pins are inserted into the outgoing STM-
1 #1. This data is clocked into the SONET/SDH framer on the rising edge of
TXTB1CLK. Bit 7 is the MSB and is transmitted first.
I
LVTTL-5sp
Telecom Bus 1 Transmit Input Clock:
All of the signals for Telecom Bus 1 are clocked into the SONET/SDH
framer on the rising edge of this 19.44 MHz clock. TXTB1CLK must be fre-
quency locked to either TXCCLK or TXCCLK if transmit retiming is not per-
formed.
TXTB1CLK
TXTB1C1J1
B01
B02
I
I
LVTTL-5sp
LVTTL-5sd
Telecom Bus 1 Transmit Input Slot Indication:
When the TXTB1SPE signal is high, TXTB1C1J1 indicates the position of
the J1 byte. When the TXTB1SPE signal is low, TXTB1C1J1 indicates the
position of the C1 byte. The J1 and C1 pulses are required if transmit retim-
ing is turned on. If transmit retiming is turned off, this signal becomes a slot
identifier.
Telecom Bus 1 Transmit Input Synchronous Payload Envelope Signal:
This signal is high for the SPE bytes and low for the TOH bytes on Telecom
Bus 1. If transmit retiming is turned off, and no J1 pulse is present in
TXTB1C1J1, then this pin can be tied low.
TXTB1SPE
TXTB1PAR
TXTB1FAIL
C03
D03
E03
I
I
I
LVTTL-5sd
LVTTL-5sp
LVTTL-5sp
Telecom Bus 1 Transmit Input Parity:
Parity for the signals of Telecom Bus1. It should be calculated by the trans-
mitting device according to the settings of the PFULL1, PEVEN1, and
PENA1 control bits in the SONET/SDH framer. Parity errors are reported
via the TB1PAR alarm bit, but no actions are taken.
Telecom Bus 1 Transmit Input Failure Indication:
TXTB1FAIL indicates that a failure has occurred on the device transmitting
on Telecom Bus 1. When TXTB1FAIL goes high, AIS-P is transmitted on
STM-1 #1/STS-3c #1.
1. When STM-4c or STS-12c frames are processed, the four transmit and four receive Telecom Buses operate in parallel as two 32-
bit wide Telecom Buses.
Pin Information
ssframer.01
8/27/99
Page 36 of 279
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