Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Signal Functional Description (Part 5 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up
3. Must pull down
4. If not used, must pull up
5. If not used, must pull down
6. Strapping input during reset; pull-up or pull-down required
Signal
Name
Description
I/OType
Notes
Data Output Mask: Same shape signal available on I/Os SDCAS1,
SDRAS1, WE1, or G_ARB after setting bits 14 and 15 of the
SDRAM0_MCCR register.
[SDDQM]
O
O
O
3.3V LVTTL
SDRAM Row Address Strobe (two signals with same shape for
buffering issues). SDRAS1 can be converted to a Chip Data Mask
(SDDQM) by setting bit 14 of the SDRAM0_MCCR register.
SDRAS0:1
3.3VLVTTL
3.3V LVTTL
Memory Write Enable (two signals with same shape for buffering
issues). WE1 can be converted to a Chip Data Mask (SDDQM) by
setting bit 14 of the SDRAM0_MCCR register.
WE0:1
PCI-32 Interface
P_ADL31:00
32-bit Multiplexed Address/Data. A write operation is defined as
the transfer of data from the PCI bus master to a PCI slave device
on the PCI Bus.
5V tolerant
3.3V PCI
I/O
5V tolerant
3.3V PCI
P_CBE3:0
P_DEVSEL
P_FRAME
Bus Command/Byte Enable.
Device Select.
I/O
I/O
I/O
O
5V tolerant
3.3V PCI
Cycle Frame. Driven by the current master to indicate the
beginning and duration of an access.
5V tolerant
3.3V PCI
P_GNT0:3
5V tolerant
3.3V PCI
PCI-32 Bus Grants.
Initiator Ready.
[P_GNT4:6]G_GNT5:7
5V tolerant
3.3V PCI
P_IRDY
P_LOCK
I/O
Lock. Used to establish, maintain, and release resource locks on
PCI-32. Reserved for future use. Tying up this signal is
recommended.
5V tolerant
3.3V PCI
I
Memory Acknowledge. Indicates that the CPC710 has flushed all
CPU to PCI-32 bus buffers and any CPU access to PCI is being
SYS_ARTRYed.
P_MEMACK
P_MEMREQ
O
3.3V LVTTL
3.3V LVTTL
Memory Request. Indicates a PCI device accessing system
memory has a potential deadlock and requests the CPC710 to
flush all posted CPU to PCI buffers and ARTRY all PCI-32 bus
transfers from the 60x bus.
I
5V tolerant
3.3V PCI
P_PAR
Parity Bit.
I/O
I/O
5V tolerant
3.3V PCI
P_PERR
PCI-32 Data Parity Error.
PCI-32 Bus Requests. P_REQ2 is sampled at Reset, to select
arbitration on the PCI-32 bus. The arbitration can be made by the
CPC710 (P_REQ2 = 1) or by external circuit (P_REQ2 = 0). In
case of external arbitration, the request is send to PCI from
P_GNT1 and the grant from the external arbiter is received on pin
P_REQ1. Extended Flash is available only when the CPC710 is
the PCI-32 arbiter.
P_REQ0:3
5V tolerant
3.3V PCI
I
[P_REQ4:6]G_REQ5:7
40
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