Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Signal Functional Description (Part 2 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up
3. Must pull down
4. If not used, must pull up
5. If not used, must pull down
6. Strapping input during reset; pull-up or pull-down required
Signal
Name
Address Retry.
Description
I/OType
Notes
Output: indicates that the CPC710 detects a condition that
requires an address tenure to be retried.
Input: When asserted in response to a CPC710 cache operation,
the CPC710 assumes the cache line is modified and/or present in
a CPU or L2 cache. The CPC710 then retries the operation on the
PCI bus and address tenure is not rerun until the device on the
PCI bus reruns its transfer. The pre-charge logic is always
signaled to initiate the pre-charge sequence.
SYS_ARTRY
I/O
2.5V CMOS
Bus Request. Indicates the device on the 60x bus associated with
this signal is requesting ownership of the address bus.
2.5V CMOS
w/pull-up
SYS_BR0:3
SYS_BG0:3
I
4
Bus Grant. Indicates the master associated with this signal may,
with proper qualification, assume mastership of the address bus.
O
2.5V CMOS
Data Bus.
Byte 0: D[0:7] - DH[0:7]
Byte 1: D[8:15] - DH[8:15]
Byte 2: D[16:23] - DH[16:23]
Byte 3: D[24:31] - DH[24:31]
Byte 4: D[32:39] - DL[0:7]
Byte 5: D[40:47] - DL[8:15]
Byte 6: D[48:55] - DL[16:23]
Byte 7: D[56:63] - DL[24:31]
2.5V CMOS
w/pull-up
SYS_DATA00:63
I/O
Data Parity Bus. Represents one bit of odd parity for each of the
eight bytes of the data bus. Odd parity means that an odd number
of bits, including the parity bit, are driven high. The signal
assignments correspond to the following:
2.5V CMOS
w/pull-up
SYS_DATAP0:7
I/O
DP[0]: Data[0:7]
DP[4]: Data[32:39]
DP[1]: Data[8:15] DP[5]: Data[40:47]
DP[2]: Data[16:23] DP[6]: Data[48:55]
DP[3]: Data[24:31] DP[7]: Data[56:63]
Data Bus Grant. Indicates the device associated with this signal
may, with the proper qualification, assume mastership of the data
bus.
SYS_DBG0:3
SYS_GBL
O
2.5V CMOS
Global. Always asserted by the CPC710 for transactions that it
initiates to indicate that all devices on the 60x bus must snoop the
transaction. Since the CPC710 asserts this signal only when it is
PowerPC bus address master, no contention is possible with
PowerPC 750 or 7400 input/output GBL signal connected to
SYS_GBL.
2.5V CMOS
w/pull-up
O.D
Hard Reset. Indicates the device or card associated with this
signal must initiate a complete hard reset. All outputs should be
released to tri-state. Duration of reset, except for device hardware
system reset, is controlled by software.
SYS_HRESET0:3
SYS_L2_HIT
O
I
2.5V CMOS
L2 Hit. Indicates an external slave has been addressed by the
current master. The CPC710 arbiter uses this signal to confirm
positive selection of an address tenure on the 60x bus.
3.3V tolerant
2.5V CMOS
4
Warning: This signal is subject to timing constraints.
37
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