Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Signal Functional Description (Part 9 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up
3. Must pull down
4. If not used, must pull up
5. If not used, must pull down
6. Strapping input during reset; pull-up or pull-down required
Signal
Name
Description
I/OType
Notes
System Reference Clock. Used as:
1. 60X bus clock
2. Attached processor clock
3. Synchronous SDRAM signals
SYS_CLK
I
3.3V LVTTL
This clock is not synchronized with the PCI-32 and the PCI-64
clocks.
Power
AV
Analog voltage—2.5V. Filtered supply for PLL circuits.
Ground.
n/a
n/a
DD
GND
n/an/a
n/a
OV
Output driver voltage—3.3V.
Logic voltage—2.5V.
n/a
n/a
DD
V
n/a
DD
Other pins
Reserved
Do not connect signals, voltage, or ground to these pins.
n/a
n/a
44
IBM [ IBM ]
