Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Signal Functional Description (Part 7 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up
3. Must pull down
4. If not used, must pull up
5. If not used, must pull down
6. Strapping input during reset; pull-up or pull-down required
Signal
G_REQ64
Name
Description
I/OType
Notes
Request 64-bit transfer. External pull-up required
I/O
3.3V PCI
Bus Requests. G_REQ2 is sampled at Reset, to select arbitration
on the PCI-64 bus. The arbitration can be made by the CPC710
(G_REQ2 = 1) or by external circuit (G_REQ2 = 0). The input
G_REQ2 must be held low in order to deselect the internal arbiter.
External logic must hold this input low for at least four (4) PCI 64
clock cycles after the rising edge of PLL_RESET. Holding
G_REQ2 low until the positive going edge of POWERGOOD is
also acceptable. In case of external arbitration, the request is sent
to PCI from G_GNT1 and the grant from the external arbiter is
received on pin G_REQ1. G_REQ5:7 are programmed by setting
bits 21:23 of the CPC0_PGCHP register
G_REQ0:4
5V tolerant
3.3V PCI
I
G_REQ5:7[P_REQ4:6]
5V tolerant
3.3V PCI
G_RESETOUT
G_RST
Local Reset. Asserted by PCI-64 reset and special conditions.
Reset PCI-64 Bus.
O.D
I/O
Input: Replicated on G_RESETOUT when programmed (no
internal use).
5V tolerant
3.3V PCI
2
Output: Activated by the CPC710 at power up or by
programming.
G_SERR
G_STOP
System Parity Error.
I/O
I/O
3.3V PCI
3.3V PCI
Stop. Asserted by the target to request the master to stop the
current transaction.
G_TRDY
Target Ready. Asserted by the target when ready to receive data.
Main clock input for the PCI-64 bit bridge (maximum 66MHz).
I/O
I
3.3V PCI
PCG_CLK
SIO Interface
3.3V LVTTL
Extended Flash Chip Enable.
This signal goes to 0 after the CPC710 has decoded an access to
the Extended Flash address range.
FLASH_CE
O
3.3V LVTTL
1: Boot Flash Enabled.
0: Extended Flash Enable. This signal must be used on card to
insure that Boot Flash and Extended Flash cannot be accessed
at the same time.
FLASH_OE
FLASH_WE
PRES_OE0:1
XADR_LAT
XCVR_RD
Output Enable. Flash ROM.
O
O
O
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Write Enable. Flash ROM.
Output Enable. Presence detect (PD) buffer 0 or buffer 1.
Latch Signal. For SIO address register.
Address Direction. SIO address bus.
42
IBM [ IBM ]
