Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Signal Functional Description (Part 4 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up
3. Must pull down
4. If not used, must pull up
5. If not used, must pull down
6. Strapping input during reset; pull-up or pull-down required
Signal
Name
Transfer Start.
Description
I/OType
Notes
Output: Indicates that the CPC710 has started an address tenure
and the address bus and transfer attribute signals are valid. Only
address-only operations and snoop operation with programmable
TT code are performed.
SYS_TS
I/O
2.5V CMOS
Input: Indicates a master on the 60x has started an address
tenure and the address bus and transfer attribute signals are valid.
For address tenures that require a data transfer, this signal also
indicates a request for the data bus.
Transfer Size.
Output signals and the TBST signal: Indicate the data transfer
size of the operation. The CPC710 sets these signals to a value
stored in the CPC0_ATAS register for the operations it initiates.
2.5V CMOS
w/pull-up
SYS_TSIZ0:2
SYS_TT0:4
I/O
I/O
Input signals and the TBST signal: For normal memory
accesses, indicate the data transfer size of the operation. For the
DMA instructions eciwx and ecowx, they indicate the 4-bit
Resource ID (RID) of the DMA operation (TBST || TSIZ0-TSIZ2).
Transfer Type.
Output: Indicates the type of transfer in progress. The values are
programmable according to the PowerPC type and stored in the
CPC0_ATAS register.
2.5V CMOS
w/pull-up
Input: Indicates the type of transfer in progress.
SDRAM Interface
BS1:0
Internal Bank Select.
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
MADDR0_EVEN
MADDR0_ODD
MADDR13:1
MDATA00:63
MDATA64:71
Memory Address bit 0 for even DIMMs.
Memory Address bit 0 for odd DIMMs.
Memory Address bits 13 to 1 (13 is msb).
Memory Data.
O
O
I/O
I/O
Memory Data ECC bits.
MUX_CLKEN1B
MUX_CLKEN2B
Clock Enable of Data sent to the Memory (two signals with same
shape for buffering issues).
O
O
3.3V LVTTL
3.3V LVTTL
Clock Enable of Data sent to the CPC710. On Clock A1 the first
part of the data is stored in the external MUX controller, and on
clock A2 full transfer is done.
MUX_CLKENA1
MUX_CLKENA2
MUX_OEA:B
MUX_SEL
Output Enable of Data to Port A or B.
O
O
3.3V LVTTL
3.3V LVTTL
Control the MUX circuit of the external MUX controller.
SDRAM Column Address Strobe
(two signals with same shape for buffering issues). SDCAS1 can
be converted to a Chip Data Mask (SDDQM) by setting bit 14 of
the SDRAM0_MCCR register.
SDCAS0:1
O
3.3V LVTTL
SDRAM Clock Enable. Ten signals with same shape for buffering
issues.
SDCKE0:9
SDCS00:11
O
O
3.3V LVTTL
3.3V LVTTL
SDRAM Chip Select.
39
IBM [ IBM ]
