Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Signal Functional Description (Part 3 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up
3. Must pull down
4. If not used, must pull up
5. If not used, must pull down
6. Strapping input during reset; pull-up or pull-down required
Signal
Name
Description
I/OType
Notes
Machine Check. Indicates that the CPC710 has detected an error
condition and a machine check exception is desired.
SYS_MCP0:3
O
2.5V CMOS
2
Notes: 1. SYS_MCP0 and SYS_MCP2 have same shape signal
2. SYS_MCP1 and SYS_MCP3 have same shape signal.
Shared.
Output: Not applicable; The CPC710 only pre-charges the signal.
SYS_SHD
I/O
O
2.5V CMOS
2.5V CMOS
Input: Instructs the pre-charge logic to initiate a pre-charge
sequence.
Soft Reset. Indicates the processor connected to this signal will
take a reset exception. Occurs following a write to the CPU soft
reset register (CPC0_SRST) that has the appropriate bit set.
SYS_SRESET0:3
Transfer Acknowledge.
Output: Indicates a single beat of data transfer between the
CPC710 and a master on the 60x bus. For read transfers,
indicates the data bus is valid with read data and the master must
latch it in. For writes, indicates that the CPC710 has latched in
write data from the data bus. The CPC710 asserts the signal for
each beat in a burst transfer.
2.5V CMOS
w/pull-up
SYS_TA
I/O
Input: Indicates a single beat of data transfer has occurred. The
CPC710 arbiter uses this signal and the address transfer attribute
signals to determine the end of the data bus tenure.
External Transfer Acknowledge Hit. A transition from high to low of
this signal results in the generation of the SYS_TA output signal in
the following system clock cycle.
SYS_TA_HIT
SYS_TBE
I
3.3V LVTTL
2.5V CMOS
2
Time Base Enable. Indicates the processor time bases should
continue counting. Reflects bit 12 of the CPC0_UCTL register.
O
Transfer Burst.
Output signal and the TSIZ signals: Indicate the data transfer
size of the operation. The CPC710 sets this signal according to
the bit in the CPC0_ATAS register for operations it initiates.
2.5V CMOS
w/pull-up
SYS_TBST
I/O
Input signal: For normal memory accesses, indicates a burst
transfer is in progress. For DMA instructions eciwx and ecowx,
the input signal and the TSIZ signals indicate the 4-bit Resource
ID (RID) of the DMA operation (TBST || TSIZ0-TSIZ2).
Transfer Error Acknowledge.
Output: Indicates that the CPC710 has detected an error
condition and that a machine check exception is desired.
Assertion of this signal terminates the current data bus tenure.
The CPC710 can be set up to transform any SYS_TEA to normal
SYS_TA with machine check condition signaling on SYS_MCP0,
SYS_MCP1, SYS_MCP2, or SYS_MCP3.
2.5V CMOS
w/pull-up
SYS_TEA
I/O
Input: Informs the CPC710 60x bus arbiter that the current data
bus tenure has been terminated.
38
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