Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Signal Functional Description (Part 8 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up
3. Must pull down
4. If not used, must pull up
5. If not used, must pull down
6. Strapping input during reset; pull-up or pull-down required
Signal
Name
Description
I/OType
Notes
JTAG Interface
3.3V LVTTL
w/pull-up
TCK
Test Clock.
I
3.3V LVTTL
w/pull-up
TDI
Test Data In.
I
O
I
TDO
TMS
Test Data Out.
Test Mode Select.
3.3V LVTTL
3.3V LVTTL
w/pull-up
3.3V LVTTL
w/pull-up
TRST
Reset.
I
System Interface
CE0_TEST
3.3VLVTTL
w/pull-down
Reserved
I
PLL_LOCK
Output indicating the PLL is locked.
O
3.3VLVTTL
PLL_RANGE1:0
PLL frequency range selector for the System Clock.
00: 50 to 100 MHz
01: 58 to 114 MHz
10: 66 to 134 MHz
11: 80 to 160 MHz
I
I
3.3V LVTTL
3.3V LVTTL
w/pull-up
PLL_RESET
Reset and Bypass mode enable of the PLL
Loop stability tuning control of the PLL.
Recommended values:
010101 if range is 50 to 100 MHz
010011 if range is 58 to 114 MHz
010011 if range is 66 to 134 MHz
010011 if range is 80 to 160 MHz
PLL_TUNE5:0
I
3.3V LVTTL
43
IBM [ IBM ]
