Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Signal Functional Description (Part 1 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up
3. Must pull down
4. If not used, must pull up
5. If not used, must pull down
6. Strapping input during reset; pull-up or pull-down required
Signal
Name
Description
I/OType
Notes
60x Interface
Check stop. Indicates that the CPC710 has detected a non-
recoverable error condition and has entered check stop state.
CHKSTOP
DLK
O
O
2.5V CMOS
3.3V LVTTL
Deadlock (DLK). Asserted when processor range of address is out
of the non-deadlock zone. An address SYS_ARTRY is sent to the
PowerPC when DLK is set.
5V tolerant
3.3 V PCI
GPIO0:2
General purpose I/O signals.
I/O
Interrupt 1. Generated after writing 1 in the PCIC1_ITADDSET
interrupt register. This interrupt can be used by an external
interrupt controller. The writing can be made from the CPU in
configuration mode or from the PCI-64 bus. Only the PowerPC
CPU can reset the interrupt by writing 1 in the
5V tolerant
3.3 V PCI
IT1
O
2
2
PCIL1_ITADDRESET interrupt reset register.
Interrupt 2. Indicates the end of the DMA data transfer.
Corresponds to assertion of bit 4 in the DMA0_GSCRx status
register.
5V tolerant
3.3 V PCI
IT2
O
I
Deadlock Disable (NODLK). Used only when the deadlock
address range checking is programmed:
3.3V LVTTL
w/pull-up
NODLK
Asserted (0), deadlock checking is disabled.
If tied high (1), deadlock checking can be performed.
Normal operation when up (1).
3.3V LVTTL
w/pull-up
POWERGOOD
SYS_AACK
I
General system reset when down (0).
Address Acknowledge. Indicates the address tenure is complete
and the ARTRY sampling window ends on the following bus cycle.
Address bus and transfer attribute signals must go to tri-state on
the next bus cycle.
O
2.5V CMOS
Address Bus.
Output: Represents the physical address of a cache operation
that should be snooped by devices on the 60x bus. A[0] is the
most significant address bit.
2.5V CMOS
w/pull-up
SYS_ADDR00:31
I/O
Input: Represents the physical address for the current
transaction.
Address Parity.
Output: Represents one bit of odd parity for each of the four bytes
of the address bus. Odd parity means that an odd number of bits,
including the parity bit, are driven high. The signals are assigned
as follows:
SYS_ADDRP0 – SYS_ADDR00:07
SYS_ADDRP1 – SYS_ADDR08:15
SYS_ADDRP2 – SYS_ADDR16:23
SYS_ADDRP3 – SYS_ADDR24:31
2.5V CMOS
w/pull-up
SYS_ADDRP0:3
I/O
Input: Represents one bit of odd parity for each of the four bytes
of the address bus. A checkstop is generated if bad parity is
detected and bit 8 is 1 in the error control register.
36
IBM [ IBM ]
