Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Signal Descriptions
The CPC710 embedded controller is packaged in a 728-ball flip-chip plastic ball grid array (FC-PBGA). The
following tables describe the package level pinout.
Pin Summary
Group
No. of Pins
Nonmultiplexed signals
Multiplexed signals
Total Signal Pins
466
10
476
40
OV
DD
V
44
81
DD
Gnd
Total Power Pins
Reserved
165
87
Total Pins
728
In the table “Signal Functional Description” on page 36, each external signal is listed along with a short
description of the signal function. Some signals are multiplexed on the same package pin (ball) so that the pin
can be used for different functions. In cases where the multiplexed signals are functionally related, they are
shown as a default signal followed by the alternate signal in square brackets (for example,
G_GNT5[P_GNT4]). To see all of the signals that are multiplexed on a single pin, see “Signals Listed
Alphabetically” on page 8. Active-low signals (for example, IT1) are marked with an overline.
It is expected that in any single application a particular pin will always be programmed to serve the same
function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise
be possible.
The Type column in “Signal Functional Description” on page 36 describes the I/O circuit type. If more detailed
information is needed, please refer to the IBM ASIC SA-12E Databook.
35
IBM [ IBM ]
