IBM PowerPC 403GCX
SRAM, ROM or I/O Burst Read with Wait and Hold
1
2
3
4
5
6
7
8
SysClk
A6:29,1
WBE2[A30],
Address4
Address1
Addr2
Addr3
WBE3[A31]
R/W
CSon=0
CSon=1
CSx5
CSon=0
OEon=0
CSon=0,1
OEon=1,0
OE4,5
BLast4
WBE0:32,3
BE0:33
Valid BE
BE
D2
BE
Valid BE
D0:31
D1
D3
D4
Error?
Error?
Error?
Error?
BusError
Hold 6
Burst + 1
Cycles
Burst + 1 Burst + 1
Cycles Cycles
Wait + 1 Cycles5
Bank Register Bit Settings
Burst
Mode
Bus
Width
Ready
Enable
Wait
States
Burst
Wait
SLF
CSon
OEon
WEon
WEoff
Hold
Bit 13
Bit 14
Bits
15:16
Bit 17
Bits
18:21
Bits
22:23
Bit 24
0 or 1
Bit 25
0 or 1
Bit 26
Bit 27
x
Bits
28:30
0 or 1
1
xx
0
0001
00
x
001
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 21 on page 37 for WBE signal definitions based on bus width.
3. WBE signals can be read/write byte enables based on the setting of IOCR[BEM].
4. When in Byte Enable Mode (IOCR[BEM] = 1), the BLast signal appears on the multiplexed OE[XSize1][BLast] out-
put, as described in Table 4 on page 9.
5. Wait must be programmed to a value ≥ (CSon + OEon). If Wait > (CSon + OEon), then all signals will retain the
values shown in cycle 3 until the Wait timer expires.
6. If Hold is programmed > 001, all output signals retain the values shown in cycle 7 until the Hold timer expires.
7. Data parity is only checked when IOCR[RDM] = 11 and BRHx[PCE] is set.
42
IBM [ IBM ]
