IBM PowerPC 403GCX
SRAM, ROM or I/O Burst Write with Wait, Burst Wait, and Hold
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SysClk
A6:29,1
WBE2[A30],
Address4
Address1
Addr2
Addr3
WBE3[A31]
R/W
CSon=0 CSon=1
CSx5
OE4,5
BLast4
CSon=0 CSon=1,0 CSon=1
WEon=0,1
WEon=0
WEon=1
WEoff=1
WEoff=1
WEoff=1
WEoff=1 WEoff=0
WBE0:32,3
BE0:33
BE
BE
Valid BE
Valid BE
CSon=0 CSon=1,0 CSon=1
OEon=0,1
OEon=0
OEon=1
Data1
Data2
Data3
Data4
D0:31
Error
?
Error
Error
Error
?
?
?
BusError
Burst + 1
Cycles
Burst + 1 Burst + 1
Cycles Cycles
Wait + 1 Cycles
Hold
Bank Register Bit Settings
Burst
Mode
Bus
Width
Ready
Enable
Wait
States
Burst
Wait
SLF
CSon
OEon
WEon
WEoff
Hold
Bit 13
Bit 14
Bits
15:16
Bit 17
Bits
18:21
Bits
22:23
Bit 24
Bit 25
0 or 1
Bit 26
0 or 1
Bit 27
Bits
28:30
0 or 1
1
xx
0
0100
01
0 or 1
0 or 1
001
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 21 on page 37 for WBE signal definitions based on bus width.
3. WBE signals can be read/write byte enables based on the setting of a control bit in the IOCR.
4. When in Byte Enable Mode (IOCR bit 20 = 0), the BLast signal appears on the multiplexed OE[XSize1][BLast] out-
put, as described in Table 4 on page 9.
5. Wait must be programmed to a value ≥ (CSon + WEon + WEoff) and ≥ (CSon + OEon + WEoff).
If Wait > (CSon + WEon) and > (CSon + OEon), then all signals retain the values shown in cycle 3 until the Wait
timer expires.
6. If Hold is programmed > 001, all output signals retain the values shown in cycle 12 until the Hold timer expires.
7. Data parity is only generated when IOCR[RDM] = 11.
43
IBM [ IBM ]
