IBM PowerPC 403GCX
SRAM Read-Write-Read with Zero Wait and One Hold
1
2
3
4
5
6
7
8
SysClk
A6:29,1
WBE2[A30],
Read Address
Write Address
Read Address
WBE3[A31]
R/W
CSx
OE4
BLast5
WBE0:32,4
BE0:35
Valid – BE
Data In
Valid – BE
Valid – BE
Data Out
Data In
D0:31
Error?
Error?
Error?
BusError
Bank Register Bit Settings
Burst
Mode
Bus
Width
Ready
Enable
Wait
States
SLF
CSon
OEon
WEon
WEoff
Hold
Bit 13
0 or 1
Bit 14
0
Bits 15:16
xx
Bit 17
0
Bits 18:23
00 0000
Bit 24
0
Bit 25
0
Bit 26
0
Bit 27
0
Bits 28:30
001
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 21 on page 37 for WBE signal definitions based on bus width.
3. Byte Enable Mode IOCR[BEM] = 1. WBE0:3/BE0:3 are byte enables and BLast is the signal which appears on the
multiplexed OE[XSize1][BLast] output.
4. When in Byte Enable Mode IOCR[BEM] = 1, the BLast signal appears on the multiplexed OE[XSize1][BLast] output,
as described in Table 4 on page 9.
5. Not Byte Enable Mode IOCR[BEM] = 0. WBE0:3/BE0:3 are write byte enables and OE is the signal which appears
on the multiplexed OE[XSize1][BLast] output.
38
IBM [ IBM ]
